Switchable‐Memory Operation of Silicon Nanowire Transistor

Abstract

of conventional memory are advantages of SRAM and DRAM over new alternatives. Therefore, they will retain their mainstream position in the memory industry for the foreseeable future. Technologies have been proposed to solve the aforementioned limitations of traditional memory devices, such as removing the storage capacitor of DRAM [16,17] and reducing the number of transistors of SRAM. [18] In this study, we demonstrate a switchable-memory transistor with a p + -i-n + doped silicon nanowire whose fabrication process is fully compatible with silicon-based complementary metal-oxide semiconductor (CMOS) technology. The outstanding memory characteristics originate from the positive feedback loop in the intrinsic channel. Notably, our single device not only reduces the number of transistors (constituting a single SRAM cell) in the memory device but also operates the switching function. This is one of the novel strengths of our switchable-memory device for future electronics, as conventional memory devices only provide the function of data storage. The decrease in the number of transistors and the operation of multiple functions can be beneficial for scaling the memory device with regard to the total chip size and power consumption. Hence, we propose a feedback field-effect transistor (FET) with a dual top-gated silicon nanowire channel to enable the switching and memory functions in a single transistor. Results and DiscussionWe demonstrate the switchable-memory characteristics of a silicon nanowire transistor with a dual-gate structure. Figure 1 shows schematic and optical images of our transistor, which consists of a silicon nanowire channel and dual-gate electrodes. On the upper side of the channel region (6 µm long), two gate electrodes (each 2 µm wide) are arranged side by side. The gate electrode located near the p + doped region is named "Gate1 (V G1 )," and the other gate electrode located near the n + doped region is named "Gate2 (V G2 )." Details regarding the fabrication are presented in Experimental Section. Our switchable-memory transistor can be fabricated using conventional CMOS technology, which is clearly advantageous for industrial applications.As shown in Figure 2a, when V DS is swept from −0.1 to 4.1 V and then back to −0.1 V as a function of V G1 and V G2 , our transistor shows bistable I DS -V DS characteristics owing to the similar structures of thin capacitively-coupled thyristor (TCCT) devices [19][20][21] and field-effect diodes. [22,23] Without gate bias voltages, the transistor exhibits ordinary p-n diode characteristics;The switchable-memory operation of a feedback silicon nanowire transistor with a dual-gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec −1 . A gate-controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more th...

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

“…When the input logic ‘00’ with V IN1 = V IN2 = − 1.0 V is applied, the two p -FBFETs are turned on, and the two n -FBFETs are simultaneously turned off. Thereafter, during the hold ‘1’ operation under zero-bias conditions, the output logic value is stored by the quasi-nonvolatile memory characteristics of the FBFETs 30 , 38 , 39 . The input logic ‘01’ operates with V IN1 = − 1.0 V and V IN2 = 1.0 V, and the output logic ‘1’ is provided.…”

Reconfigurable Logic‐in‐Memory Using Silicon Transistors

“…[24][25][26][27] Specifically, switchable memory operations in silicon transistors demonstrate the possibility of a dual function of memory and logic. [28] Recently, applications in logic-in-memory have been investigated via computer simulations. [29] In addition, silicon transistors based on positive feedback mechanisms enable fine-grain-reconfigurable electronics because they use both electrons and holes to conduct current.…”

NAND And NOR Logic-In-Memory Comprising Silicon Nanowire Feedback Field-Effect Transistors

“…The operation principle of the pand n-FBFETs is based on a positive feedback loop mechanism in the channel regions [29][30][31] . The FBFETs consisting of p + -n + -p + -n + regions have two potential barriers in the channel regions, and the potential barrier heights are controlled by the presence or absence of charge carriers in the potential well.…”

“…When the input logic '00' with V IN1 = V IN2 = −1.0 V is applied, the two p-FBFETs are turned on, and the two n-FBFETs are simultaneously turned off. Thereafter, during the hold '1' operation under zero-bias conditions, the output logic value is stored by the quasinonvolatile memory characteristics of the FBFETs 30,35,36 . The input logic '01' operates with V IN1 = −1.0 V and V IN2 = 1.0 V, and the output logic '1' is provided.…”

“…In this study, we propose a NAND and NOR LIM composed of silicon nanowire (SiNW) feedback eldeffect transistors (FBFETs) to verify universal gate functions, where the con guration of the SiNW FBFETs maintains conventional CMOS logic gates. The SiNW FBFETs utilized in the LIM have demonstrated near-zero subthreshold swings (SS), high speed, low operating voltage, and quasinonvolatile memory characteristics based on the positive feedback loop mechanism [29][30][31] . The LIM exhibits a high processing speed close to that of SRAM and DRAM (<5 ns), ultra-low standby power while storing the data, retention characteristics that will retain certain computational logic states without power supply, and relatively low operating voltage (≤2.5 V) compared to ash memory.…”