Demonstration of highly scaled FinFET SRAM cells with high-&amp;#x03BA;/metal gate and investigation of characteristic variability for the 32 nm node and beyond

Kawasaki, Hiromu; Khater, Marwan; Guillorn, Michael A.; Fuller, N.; Chang, J.; Kanakasabapathy, S.; Chang, Leland; Muralidhar, R.; Babich, Katherina; Yang, Qingchao; Ott, J. A.; Klaus, D.; Kratschmer, E.; Sikorski, E.; Miller, Robert J.; Viswanathan, R.; Zhang, Y.; Silverman, J. P.; Ouyang, Q.; Yagishita, Akira; Takayanagi, Motowo; Haensch, Wilfried; Ishimaru, K.

doi:10.1109/iedm.2008.4796661

Cited by 59 publications

(35 citation statements)

References 2 publications

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“…Fin patterning based on spacer technology has been proposed for fine Fin control [117] . Novel SiBCN low K spacer technology and spacer removal method have been demonstrated as examples for parasitic capacitance reduction [124,125] .…”

Section: Non-planar Finfetmentioning

confidence: 99%

“…In the demonstrated FUSI integration scheme, a Ni-FUSI process on HfO 2 dielectrics incorporating with doping and ultra-thin cap layer techniques to tune the WF of Ni-FUSI to the Si conduction band edge was demonstrated for low V t applications. Besides, IBM also reported the integration process of high K gate dielectric and a single metal gate (HKMG) with mid-gap work function for sub-32 nm FINFET CMOS technology [49] .…”

Section: New-generation High K and Metal Gate Transistor Technology Fmentioning

confidence: 99%

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Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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Section: Non-planar Finfetmentioning

confidence: 99%

Section: New-generation High K and Metal Gate Transistor Technology Fmentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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“…Layout dimensions for 22nm (25nm drawn gate length) 6-T SRAM cells were selected based on recent publications [6][7][8][9][10] and are summarized in Table I for a conventional notched cell layout. The quasi-planar bulk MOSFET design was optimized via 3-D device simulations to achieve the highest I ON for I OFF = 3nA/um, at V dd = 1V: electrical channel length (distance between the points where the source/drain doping profiles fall to 2×10 19 cm -3 ) L eff = 27nm; effective oxide thickness EOT = 9Å; source/drain extension junction depth X J,ext = 10nm.…”

Section: Nm Bulk Sram Cell Design Studymentioning

confidence: 99%

Tri-gate bulk CMOS technology for improved SRAM scalability

Shin

Nikolić

Liu

et al. 2010

2010 Proceedings of the European Solid State Device Research Conference

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-A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling. I. INTRODUCTIONA challenge for continued SRAM scaling is threshold voltage (V T ) mismatch due to process-induced variations [1], which degrades the minimum operating voltage (V min ) of an SRAM array [2]. To address this challenge, an improved transistor design that provides for reduced short-channel effects (i.e., improved gate control over the channel potential) is required. The quasi-planar tri-gate bulk MOSFET [3] is an example of such a design; it utilizes a gate electrode that is physically wrapped around the top portion of the channel region to provide for greater capacitive coupling between the gate and the channel region [4]. In this work, a timed etch in dilute hydrofluoric (HF) acid solution is used to recess the isolation oxide prior to gate-stack formation, to form quasiplanar bulk MOSFETs using an otherwise conventional fabrication process flow.Improvements in transistor performance and SRAM yield are demonstrated in an early 28nm CMOS technology. The benefits of quasi-planar bulk MOSFET technology for voltage and area scaling are then assessed using three-dimensional (3-D) device simulations with atomistic doping profiles and analytical modeling to estimate 6T-SRAM cell yield for 22nm CMOS technology.

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“…15 demonstrates that this can enable significant yield enhancement and voltage reduction for 6T-SRAM; implemented in an 8T-SRAM cell, maximum voltage scalability could be attained. These thin-body device structures could thus be an ideal solution for SRAM scaling [30]. However, since the performance of these device structures often suffers from parasitic resistance and capacitance [31], there may be a divergence between logic performance needs and memory yield requirements such that a hybrid technologyVtraditional MOSFET structures for logic and thin-body structures for SRAMVmay become a desirable option.…”

Section: B Low-voltage Cachesmentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

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| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

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Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond

Cited by 59 publications

References 2 publications

Challenges of 22 nm and beyond CMOS technology

Challenges of 22 nm and beyond CMOS technology

Tri-gate bulk CMOS technology for improved SRAM scalability

Practical Strategies for Power-Efficient Computing Technologies

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