FinFET performance advantage at 22nm: An AC perspective

Guillorn, Michael A.; Chang, Josephine; Bryant, A.; Fuller, N.; Dokumaci, O.; Wang, X.; Newbury, J.; Babich, Katherina; Ott, J. A.; Haran, Bala; Yu, Roy; Lavoie, C.; Klaus, D.; Zhang, Y.; Sikorski, E.; Graham, William P.; To, B.; Lofaro, M.; Tornello, J. A.; Koli, Dinesh; Yang, Bo; Pyzyna, A.; Neumeyer, D.; Khater, Marwan; Yagishita, Akira; Kawasaki, Hiromu; Haensch, Wilfried

doi:10.1109/vlsit.2008.4588544

Cited by 73 publications

(32 citation statements)

References 2 publications

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“…Parasitic capacitances and access resistances must also be closely monitored since both are strongly linked to the device architectures and isolation schemes (SOI BOX vs. STI) [9]. In addition, these are also expected to play an important role in the ESD robustness.…”

Section: Introductionmentioning

confidence: 99%

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Chiarella

Witters

Mercha

et al. 2010

Solid-State Electronics

123

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Section: Introductionmentioning

confidence: 99%

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Chiarella

Witters

Mercha

et al. 2010

Solid-State Electronics

123

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“…Some papers reported how to estimate parasitic resistance and capacitance [18]- [22] in scaled MOSFETs. We calculated the transconductance and the gate capacitance based on these paper and estimated f T and f max of FinFET.…”

Section: Rf Performancementioning

confidence: 99%

Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Ohguro

Inaba

Kaneko

et al. 2015

IEICE Trans. Electron.

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SUMMARY In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H 2 annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f T and f max , it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.

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“…These thin-body device structures could thus be an ideal solution for SRAM scaling [30]. However, since the performance of these device structures often suffers from parasitic resistance and capacitance [31], there may be a divergence between logic performance needs and memory yield requirements such that a hybrid technologyVtraditional MOSFET structures for logic and thin-body structures for SRAMVmay become a desirable option.…”

Section: B Low-voltage Cachesmentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

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| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

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FinFET performance advantage at 22nm: An AC perspective

Cited by 73 publications

References 2 publications

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Practical Strategies for Power-Efficient Computing Technologies

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