A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units
(i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been
proposed in the literature. However, only single port memory is considered for register allocation and no efficient
synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but
also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed
technique can also be applied to multiport memory synthesis in which the maximum number of read ports is
different from the maximum number of write ports. Therefore, the entire design space is explored and has the
capability to handle early architectural design exploration so that the quality of designs produced by an automatic
synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this
method to different synthesis examples are presented. Results and improvements over previous techniques are
demonstrated. A key element in our approach is the successful adoption of techniques originally developed for
problems in test generation to the field of memory synthesis.
ModemVLSI circuits with extensive built-in self-test (JUST) resources have the problem of long testing time if the testing for the different parts of the circuits are executed successively.Herein, we present a heuristic solution, called Weighted Cluster Partitwning (WCP), to the problem of long testing time for VLSI circuits.Some of the techniques in current use exploit parallelism in testing VLSI circuits, but the computation is quite expensive.Our solution is a more efficient and effective procedure which explores the space of concurrent test schedule and leads to a considerable reduction of testing time by suitable incorporation of BIST in the circuit.
A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-tothermometric converter, of which the critical path delay was optimized from 355 to 157 ps which accounts for a 55.77% delay improvement, and the delay uncertainty due to process variation was optimized by 60.75%. A 4-b unity weight binary-to-thermometric converter was also optimized, of which the critical path delay was reduced from 152 to 103 ps which accounts for a 32.23% delay improvement, and delay uncertainty was optimized by 63.6%. Applying the proposed timing optimization algorithm to a mixed-dynamic-static CMOS 64-bit adder, the critical path delay and the power-delay-product were optimized to 632 ps and 84.17 pJ, respectively.
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