Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS

Wang, Mingzhen; Chen, Chien‐In Henry; Radhakrishnan, S.

doi:10.1109/tim.2006.887404

Cited by 25 publications

(13 citation statements)

References 23 publications

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“…The power efficiency is 5mW/GS/s, which is better than previously-reported ADCs operating at similar speeds with a traditional clock distribution network as can be seen by the comparison to other recently published 5-bit flash ADC architectures [9], [10], [11] in Fig. 12.…”

Section: Power Consumptionsupporting

confidence: 50%

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

Bichan

Dunwell

Wang

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that the SNDR penalty introduced by this effect can become significant at high frequencies. To address this issue, a passive resonant clock network is proposed to distribute the clock to the comparators in a flash ADC. The inductive termination of this network serves to resonate out the parasitic and input capacitances of the ADC, allowing for a 2.5-GHz clock signal to be conveyed to a load of 256 comparators while consuming less power than traditional clock networks due to the reduced number of active clock buffers required. This clock network produces little timing skew at the resonant frequency, thereby obviating the need for a track-andhold amplifier, which further reduces the power requirements of the ADC. This clock network was implemented in a 5-bit flash ADC designed in 65 nm CMOS, with a measured SNDR of 26 dB.

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Section: Power Consumptionsupporting

confidence: 50%

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

Bichan

Dunwell

Wang

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The one out of n codes is then converted to binary code d2, d1, d0 by Read only memory (ROM) encoder, as shown in Fig.5. [35]. The ROM encoder is a common and straight forward approach to encode the one out of n code to binary bit.…”

Section: Thermometer Code Convertermentioning

confidence: 99%

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

Sunaniya¹,

Khare²

2013

IJCA

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The Analog to Digital converters (ADC) play a very important role in today's world of electronic systems. The requirement of present applications demands high speed, low power dissipation, minimum area, low noise and application specific resolution. Out of the various types of ADCs available the flash ADC is most popular for its highest conversion rate and its wide applications. On the down side the flash ADC dissipates high power due to the presence of resistance ladder. The power dissipation further increases with increase in resolution. In this research two different approaches are presented which eliminates the resistor ladder completely and hence reduce the power demand drastically. The first approach is Switched Inverter Scheme (SIS) ADC; it is realized for 3 bits using 7 comparator circuits of varying size in CMOS 45nm technology with Predictive Technology Model (PTM). The test result obtained indicates an offset error of 0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of 0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 µwatts; Power delay product (PDP) is 415.9 fWs, and the area overhead is 1.89µm 2 . The second approach is Sleep transistor SIS ADC. This approach shows 71% improvement in power dissipation. Whereas PDP is found to be 107.3 fWs and area overhead is 1.94 µm2 for Sleep transistor SIS ADC.

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“…In order to bridge the link between the real world and the digital world ADCs are widely used [2]. Successive approximation analog-to-digital convertors (SA-ADCs) are a class of ADCs in which the convergence to the final digital output code occurs after a binary search through all possible quantization levels.…”

Section: Introductionmentioning

confidence: 99%

Elimination of false codes in an asynchronous parallel successive approximation A/D converter

Venkataraman

Furth

Pakala

2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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We report on a scheme to eliminate false codes generated due to switching delays among the output bits of an asynchronous parallel successive approximation analog-todigital converter (SA-ADC) developed by Lin and Liu [1]. False output codes are eliminated by converting the binary outputs to Gray codes. A novel asynchronous parallel gray-to-binary converter is introduced to effectively reduce switching delays from 10.0 -26.5 ns to 767 -962 ps, when operating with a 50 kHz triangular input and 2V power supply. Simulated INL and DNL are less than ± 0.4 LSB and ± 0.45 LSB, respectively, at 800 µW of power consumption. Measurement results of the ADC, fabricated in 0.5-µm CMOS technology, show the efficacy of the proposed scheme to remove false codes.

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Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS

Cited by 25 publications

References 23 publications

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

Elimination of false codes in an asynchronous parallel successive approximation A/D converter

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