Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations

Yelamarthi, Kumar; Chen, Chien‐In Henry

doi:10.1109/tsm.2012.2185961

Cited by 8 publications

(3 citation statements)

References 23 publications

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“…Following the traditional approach [12,13], statistical analysis was performed through 1000 runs of Monte Carlo simulations to measure, for each output signal, standard deviation (s t ), mean (m t ) and 3-sigma delay limit (t W ) calculated as t + 3 t . The latter was referenced as a bench mark in the comparison since, as explained in [21], taking the effects of process variations into account, 99.7% of the samples will show a delay between t À 3 t and t + 3 t .…”

Section: Performance Analysis and Comparison Resultsmentioning

confidence: 99%

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Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

Perri

Lanuzza

Corsonello

2013

Circuit Theory & Apps

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This paper presents a novel approach to design high-speed low-power parallel-prefix adder trees. Sub-circuits typically used in the design of parallel-prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy-delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower.A 32-bit Brent-Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average.

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Section: Performance Analysis and Comparison Resultsmentioning

confidence: 99%

“…S. PERRI, M. LANUZZA AND P. CORSONELLO in [21], taking the effects of process variations into account, 99.7% of the samples will show a delay between t À 3 t and t + 3 t .…”

mentioning

confidence: 99%

Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

Perri

Lanuzza

Corsonello

2013

Circuit Theory & Apps

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“…Over the last decade there were many algorithms proposed for transistor sizing of the dynamic CMOS circuits to give better timing optimization. Timed Logic Synthesizer (TILOS) was an algorithm which performed sizing of the transistors iteratively based on a fixed ratio [3]. The sizing of the transistors was done only on the critical paths.…”

Section: Introductionmentioning

confidence: 99%

High Performance Low Leakage Power Full Subtractor Circuit Design Using Rate Sensing Keeper

Sivaranjani¹

2014

IJRET

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Dynamic CMOS are widely employed in high-performance CMOS chips due to high speed and less area in comparison with Static CMOS. However, Dynamic CMOS circuits are inherently less noise tolerant than Static CMOS circuits. This problem becomes more severe with aggressive technology scaling into nanometer process, particularly caused by the charge sharing, the sub-threshold leakage current, the power rail noise and the crosstalk noise. Both noise and process variations impact reliability, causing logic errors that can result in system failure. Process variation is defined as "the deviation from intended or designed values for a structure or circuit parameter of concern" parameter of concern". In this project, a full subtractor circuit is designed and simulated using rate sensing keeper technique with 120nm technology and V dd =1.2V for improving the timing and noise tolerance also the noise tolerance characteristics of the full subtractor circuit designed using Rate Sensing Keeper is compared with Twin-Transistor, Current Mirror Keeper based full subtractor circuit.

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Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

Wey

Chang

Liao

et al. 2014

Circuit Theory & Apps

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SummaryIn this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.

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Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations

Cited by 8 publications

References 23 publications

Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

High Performance Low Leakage Power Full Subtractor Circuit Design Using Rate Sensing Keeper

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

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