Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

Abstract

This paper presents a novel approach to design high-speed low-power parallel-prefix adder trees. Sub-circuits typically used in the design of parallel-prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy-delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower.A 32-bit Brent-Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average.

Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

“…(18). The hybrid Type 1 RCA/HCLA n M delay is related to evaluating the carry signals c 0 -c M À 1 .…”

“…Using Eq. (18), and the specific structure of hybrid RCA/HCLA adders, the area complexity of the Type 2 RCA/HCLA n M design is obtained with reference to Fig. 13 as…”

“…The discussed six different types of adders and previously published efficient adders of [16][17][18] were implemented in VHDL at the register transfer level and synthesized for both cases M ¼32, n ¼6 and M¼64, n¼ 8 using Nangate 45 nm Open Cell Library. We used Synopsys synthesis tools package 2005.09-SP2.…”

“…The literature gives a variety of solutions for optimizing adders using different techniques such as carry-select adders [11][12][13], carry save adders [14], carry lookahead adders [15][16][17][18], hybrid between carry-select and carry-lookahead adders [19][20][21][22][23][24], carry skip [25,26], and conditional-sum adders [27,28].…”

“…3. The carry-in signals fed to the S & C blocks of RCA adders in Stage 3 are coming from the carry-out signals of the 3-bit HCLA modules in Level 1 of the hierarchical adder.Using Eq (18),. and the specific structure of the hybrid RCA/ HCLA adders, the area complexity of the Type 1 RCA/HCLA A hybrid RCA/HCLA 16-bit adder based on radix-4 HCLAs (RCA=HCLA16 4 ).…”