Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

Ibrahim, Atef; Gebali, Fayez

doi:10.1016/j.mejo.2015.06.008

Cited by 18 publications

(20 citation statements)

References 25 publications

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“…The structure of the 64-bit adder of [29] From (18) and (12), it can be concluded that the proposed adder is much faster than [29]. The hardware requirements of [29] can be estimated as: In the previous equation, for the first block, only the generation of the g signal is considered (for the all the adders in this paper, we assume that C in = 0). We also disregard the computation of p and g for the last block (we eliminate the parts of the circuit that calculate C out in all adders to perform a fair comparison).…”

Section: Discussionmentioning

confidence: 99%

“…In [29], carries are partially computed from a Carry-Look-ahead structure: Transistor count comparison is herein performed by counting the number of transistors required to implement each digital gate. We considered complementary metaloxide semiconductor (CMOS) designs for all the required gates.…”

Section: Discussionmentioning

confidence: 99%

“…A NOT gate requires two transistors, and six transistors are required for each two-input AND and OR gate. From (13), (15), (17), and (19), the total number of transistors is 5540, 7692, 9218, and 4792 for the proposed adder, [28], Kogge-Stone, and [29], respectively. Therefore, except for [29], which is implemented with about 13% less transistors, the proposed adder requires in average around 52% less transistors than the other adders in the state-of-the-art.…”

Section: Discussionmentioning

confidence: 99%

“…In order to increase the performance of the addition of large numbers, hybrid adders have been suggested, since the regular horizontal extension of conventional architectures such as parallel-prefix and carry-select adders leads to excessive power-consumption. In this direction, recently, 64 and 128-bit adders using PPF, CSL, and CSK adders have been presented in [28], while in [29], ripple carry and CLA adder structures were combined. The adder structures of [30] use carry save adders and CLA, and, in [31], CSL is applied in conjunction with the Kogge-Stone structure.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

New energy‐efficient hybrid wide‐operand adder architecture

Jafarzadehpour

Molahosseini

Zarandi

et al. 2019

IET Circuits, Devices & Systems

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The consumer electronics markets have increased the demand for high-speed and low-power adders with large operands to be integrated in modern portable systems. Traditional fast adder architectures, such as parallel-prefix adders, exhibit high-power consumption for large operands. The hybrid design is one of the most promising techniques to achieve a trade-off between the delay and power-consumption for the addition of large operands. This study presents a new hybrid adder architecture, specifically designed for large operands, based on the premise that in large parallel-prefix adders the leastsignificant carries are produced much sooner than the most-significant ones. Therefore, the authors avoid the incorporation of fast architectures related with the application of carries to the final summation least-significant bits, with no impact on the critical path. This leads to a reduction in the area of the summation blocks in the least-significant positions without compromising the speed. Moreover, the complement of the carries is generated and propagated inside the carry network of the proposed adder in order to decrease the delay. VLSI implementation results on the 65-nm-TSMC technology show that the proposed adder achieves >25% of energy savings, and a reduction of over 30% of the area-delay-product in comparison with state-of-the-art wide-operand adders.

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