A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder

Hasan, Mehedi; Hossain, Muhammad Saddam; Siddique, Abdul Hasib; Hossain, Mainul; Zaman, Hasan U.; Islam, Sharnali

doi:10.1016/j.mejo.2021.104992

Cited by 21 publications

(20 citation statements)

References 23 publications

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“…A majority function provides logic 1 if more than half of the input signals are logic 1. For a 3-input majority gate, the logic function can be expressed as follows [21]:…”

Section: Qca Logic Gatesmentioning

confidence: 99%

“…As per the analysis conducted in Section 3.1, it can be observed that majority gate and inverter are the major components in the QCA FA design. As stated in [21], the carry-output bit of a 1-bit FA follows the logic characteristics of a 3-input Majority Gate. Hence, for the QCA FA design, the carry-out bit can be implemented with a single 3-input majority gate.…”

Section: General Logic Designmentioning

confidence: 99%

“…In binary addition, full adder (1-bit adder) is considered the basic unit cell [19,20]. Moreover, wide word length adders are mainly implemented based on a 1-bit FA cell [21,22]. In addition, diferent arithmetic functions need addition in their internal nodes.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Joy

Chakraborty

Islam

et al. 2023

Advances in Materials Science and Engineering

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Being one of the promising techniques for future computing systems, quantum-dot cellular automata (QCA)-based circuit design has gained massive interest among researchers due to which numerous QCA-based full adder (FA) circuits have been designed. Due to numerous QCA FA circuits available in the existing literature, researchers find it difficult to invest the time to search, implement, simulate, and analyze QCA FAs to find the best-suited design according to their needs. Existing review articles do not present a complete overview and performance comparison of QCA FAs. Also, the existing articles do not include quite a number of QCA FA designs in the literature review. As a result, a detailed review including all possible QCA FAs becomes essential. Therefore, rather than going for a new QCA FA design, this research aims to aid researchers by providing an extensive literature review and comprehensive study on existing QCA FAs. A total of 47 QCA FAs have been considered for analysis. The QCA FA implementation method and performance parameters are summarized in a tabular manner to provide a quick overview and comparison of the QCA FAs.

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“…A majority function provides logic 1 if more than half of the input signals are logic 1. For a 3-input majority gate, the logic function can be expressed as follows [21]:…”

Section: Qca Logic Gatesmentioning

confidence: 99%

Section: General Logic Designmentioning

confidence: 99%

See 1 more Smart Citation

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Joy

Chakraborty

Islam

et al. 2023

Advances in Materials Science and Engineering

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“…Two 4‐bit CLA unit cells without utilizing

{G}_i

and

{P}_i

terms are portrayed in Refs. 30,31. The circuits in Refs.…”

Section: Literature Review Of Existing 4‐bit Clamentioning

confidence: 99%

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Hasan

Chowdhury

Faruqe

et al. 2023

Engineering Reports

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This research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

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“…The performance of arithmetic circuits determines the overall performance of a digital processor [3]. The addition operation plays a fundamental role because several complex operations are dependent on addition [4,5].…”

Section: Introductionmentioning

confidence: 99%

A high‐performance full swing 1‐bit hybrid full adder cell

Hussain

Hasan

Agrawal

et al. 2021

IET Circuits, Devices & Syst

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This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.

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A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder

Cited by 21 publications

References 23 publications

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

A high‐performance full swing 1‐bit hybrid full adder cell

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