A high‐performance full swing 1‐bit hybrid full adder cell

Abstract

This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.

Design of an automatic gain control loop for high speed communication

“…Power consumption is another parameter of integrated circuits. [19][20][21] The power consumption of this AGC loop is high due to the fact the output is a 100 Ω differential load. Because of this, the second FGA has a high-power consumption.…”

“…Also, the AGC loop shows a high bandwidth of 1–30 GHz. Power consumption is another parameter of integrated circuits 19–21 . The power consumption of this AGC loop is high due to the fact the output is a 100 Ω differential load.…”

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

“…The 1‐bit carry generator unit is taken from Ref. 34. Therefore, the operation principle of the 1‐bit carry generator used in the proposed architecture can be understood from Ref.…”

“…Therefore, the operation principle of the 1‐bit carry generator used in the proposed architecture can be understood from Ref. 34. Schematic of the 1‐bit carry generator unit is shown in Figure 3.…”

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

“…In ALU design, addition is a fundamental operation [17,18]. In binary addition, full adder (1-bit adder) is considered the basic unit cell [19,20]. Moreover, wide word length adders are mainly implemented based on a 1-bit FA cell [21,22].…”