New energy‐efficient hybrid wide‐operand adder architecture

Abstract

The consumer electronics markets have increased the demand for high-speed and low-power adders with large operands to be integrated in modern portable systems. Traditional fast adder architectures, such as parallel-prefix adders, exhibit high-power consumption for large operands. The hybrid design is one of the most promising techniques to achieve a trade-off between the delay and power-consumption for the addition of large operands. This study presents a new hybrid adder architecture, specifically designed for large operands, based on the premise that in large parallel-prefix adders the leastsignificant carries are produced much sooner than the most-significant ones. Therefore, the authors avoid the incorporation of fast architectures related with the application of carries to the final summation least-significant bits, with no impact on the critical path. This leads to a reduction in the area of the summation blocks in the least-significant positions without compromising the speed. Moreover, the complement of the carries is generated and propagated inside the carry network of the proposed adder in order to decrease the delay. VLSI implementation results on the 65-nm-TSMC technology show that the proposed adder achieves >25% of energy savings, and a reduction of over 30% of the area-delay-product in comparison with state-of-the-art wide-operand adders.

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

“…With regard to performance in Tab. 2, there is a strong explanation that, in comparison with [27,17,28], the proposed 32-bit KS-CLS adder will improve the energy by approximately 43%. The improvements of the Area-Delay Product (ADP) are about 1952.43, and 53% when compared to [17], and [28], respectively.…”

“…2, there is a strong explanation that, in comparison with [27,17,28], the proposed 32-bit KS-CLS adder will improve the energy by approximately 43%. The improvements of the Area-Delay Product (ADP) are about 1952.43, and 53% when compared to [17], and [28], respectively. The proposed 32bit adder not only has less delay but also enhances the energy consumption and the circuit area.…”

“…The Area-Delay Product (ADP) updates are about 3216 while the Power Delay Product (PDP) is around 0.031 as opposed to other current adder and hybrid Kogge-Stone adders. Since a detailed examination, Hybrid KS-CLA, KS-CSlA, HC Adder [27], Hybrid HC Adder [27], Hybrid Sum Producer [17], Kogge-Stone [b], PPF/CSSA4_4 [17], and PPF/CSSA6-3 [28] are also considered. In addition, a comprehensive evaluation will be performed.…”

“…Therefore, preparing competent adders may result in the improvement of the presentation and a decrease in the power of processors. Several concurrent and equivalent structure-dependent systems have often been suggested to enhance different parameters [16,17].…”

High speed modified carry save adder using a structure of multiplexers

“…It is becoming increasingly important to enhance the data path units' performance to meet grows of high performance processor. The use of the adder unit in implementing most arithmetic operations increases the need to have low power, high speed and small area design of adder [1][2][3][4][5][6][7]. Adders are primarily used as basic units in implementing digital signal processing (DSP) systems for applications like design of analog to digital converters (ADCs) and design of digital filters [8][9][10][11][12][13].…”