Graph partitioning for concurrent test scheduling in VLSI circuit

Abstract

ModemVLSI circuits with extensive built-in self-test (JUST) resources have the problem of long testing time if the testing for the different parts of the circuits are executed successively.Herein, we present a heuristic solution, called Weighted Cluster Partitwning (WCP), to the problem of long testing time for VLSI circuits.Some of the techniques in current use exploit parallelism in testing VLSI circuits, but the computation is quite expensive.Our solution is a more efficient and effective procedure which explores the space of concurrent test schedule and leads to a considerable reduction of testing time by suitable incorporation of BIST in the circuit.

BIST hardware synthesis for RTL data paths based on test compatibility classes

“…To overcome the fixed test resource allocation, simultaneous test hardware insertion and test scheduling was proposed in [19]. While previous test scheduling algorithms [20][21][22] assumed fixed test resource allocation, the work in [19] presented an incremental test scheduling procedure which overcomes the limited testable design space exploration encountered with fixed test resources. Despite its good performance, the algorithm in [19] is not capable of dealing in low computational time with complex designs such as 32-point discrete cosine transform (DCT), since a branch and bound-based algorithm is employed to explore the testable design space.…”

“…The previous approaches [24][25][26][27][28][29] proposed separate solutions for solving only one of the problems (a) -(c) at the expense of the other problems of the BIST embedding methodology. Furthermore, the interrelation between test synthesis and test scheduling which leads to huge size of the testable design space (problem d) was not solved efficiently by the previously described approaches [17][18][19][20][21][22] which trade-off the quality of the final solution and computational time.…”

Efficient BIST hardware insertion with low test application time for synthesized data paths

“…A different approach based on simultaneous test hardware insertion and test scheduling at RTL is presented in [5]. While previous test scheduling approaches [6,7,8] assume fixed test resource allocation which implies that the test hardware is allocated before the test scheduling process, this work presents an incremental test scheduling procedure where test scheduling is performed concurrently with test hardware allocation. A branch and bound technique is employed during the exploring process to prune the design space.…”