The authentication based on the passwords is used mostly in applications for the computer security and privacy. However, the human actions such as selecting less secured passwords credentials and inputting passwords in an insecure way are considered "the weakest link" within the authentication chain. Instead of arbitrary alphanumeric strings, users tend to select passwords either short or purposeful for simple memorization. With internet applications and mobile apps pile up, individuals will access these applications anywhere and anytime with different devices. This evolution brings good convenience however it will increases the probability of exposing passwords credentials to shoulder surfing attacks. Attackers will observe directly or use external recording devices to get users' credentials. To overcome this issue, proposed a novel authentication system named PassMatrix, which is based on graphical passwords to resist shoulder surfing attacks. With a one-time valid login indicator and change of location horizontal and vertical bars covering the complete scope of pass-images, PassMatrix offers no hint for attackers to work out or narrow down the password even they conduct multiple camera-based attacks. Implemented a PassMatrix prototype on web applications and allotted real user experiments to describee its memorability and usefulness. From the experimental result, is shown that, the proposed system achieves better resistance to shoulder surfing attacks whereas maintaining usability.
a first-reported 4Kx2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted memory management unit (W-MMU) and multistandard architecture reduce DRAM bandwidth and cost by 43% and 28%, respectively. This 4K Main-10 HEVC video decoder chip integrates 3.4M gate counts with area of 2.86mm 2 . It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [6] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback for UHD-TV applications.
I.P 0 P 1 P 2 P 3 WORD Address 0 4 P 2 P 3 WORD Address BIT Address B 0 B 7 …… DA = 1 WA = 1, BA = 2
A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of web's video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm 2 of core area. Several area-efficient techniques are realized, leading to 43.6% of area reduction. A new rate control is designed to facilitate the adaptation of video data and frame rates for network services. Two fast algorithms and new bool encoder/decoder are proposed to enhance power efficiency. This chip consumes 28.15mW and 10.02mW of VP8 encoder and decoder average power for 1080p@30fps at 0.9V, respectively.
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm 2 . This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-ratedistortion optimization (RDO) processes and reduces external bandwidth via line-store SRAM pool (LSSP) and data-bus translation (DBT) techniques. For smartphone applications, it completes real-time HEVC encoding and decoding with 4096×2160 resolution and 30fps, and consumes 126.73mW (0.5nJ/pixel) of core power dissipation at 0.9V, at 494MHz (encoding) and 350MHz (decoding). 1080HD and 720HD resolutions are reported as well. The chip features are summarized in Fig. 18.6.1.
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