A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

Chen, Ju; Liu, Tsu-Ming; Chang, Yung-Chang; Wang, Chih–Ming; Lin, Hue-Min; Cheng, Chia-Yun; Chen, Chun-Chia; Chiu, Min-Hao; Wang, Sheng-Jen; Chao, Ping; Hu, Meng-Jye; Yeh, Fu-Chun; Chuang, Shun-Hsiang; Lin, Hsiu-Yi; Wu, Ming-Long; Chen, Che‐Hong; Tsai, Chung-Hung

doi:10.1109/esscirc.2014.6942055

Cited by 10 publications

(4 citation statements)

References 7 publications

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“…Performances are obtained thanks to a efficient pipeline scheme, a specific cache for the motion compensation filter and a unified prediction engine supporting hierarchical coding structure and many prediction and transform block sizes. In [15], an HEVC decoder supporting 4K resolution at 60fps is proposed and results are given for a 28 nm CMOS technology. The clock frequency is set to 350 MHz.…”

Section: Low Power Hevc Decodersmentioning

confidence: 99%

Low power HEVC software decoder for mobile devices

Raffin

Nogues

Hamidouche

et al. 2015

J Real-Time Image Proc

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In the context of mobile handheld devices, energy consumption is a primary concern and the process of video decoding is often among the most resource-intensive applications. Recent embedded processors are equipped with advanced features such as dynamic voltage frequency scaling (DVFS) in order to reduce their power consumption. These features can be used to perform low power video decoding when no hardware decoding support is available for a given standard. High efficiency video coding (HEVC) is a recent video standard offering state-of-the-art compression rates and advanced parallel processing solutions. This paper presents strategies for the power optimization of a real-time software HEVC decoder on NEON architecture. These strategies include the exploitation of data and task-level parallelism, as well as the use of a new frequency control system to optimize the processor DVFS, based on an estimation of the decoding complexity. Extensive power measurement results, based on a multi-core ARM big.LITTLE processor, are provided and compared to state-of-the-art. These results show that the proposed open-source implementation can reach an energy consumption below 21 nJ/px for HD decoding at 2.2 Mbits/s.

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Section: Low Power Hevc Decodersmentioning

confidence: 99%

Low power HEVC software decoder for mobile devices

Raffin

Nogues

Hamidouche

et al. 2015

J Real-Time Image Proc

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“…Recently, several hardware [18]- [22] and software [12], [23]- [26] HEVC decoders have been developed. The hardware solutions offer a fast HEVC decoder implementation enabling real time decoding of 4Kp60 [19] and even 8Kp60 [21] with a very low energy consumption performance [20]. On the other hand, software HEVC decoder implementations offer flexibility, fast time-to-market and are well suited for quick adaptation to standard evolutions.…”

Section: B Real Time Video Codecsmentioning

confidence: 99%

4K Real Time Software Solution of Scalable HEVC for Broadcast Video Application

Parois¹,

Hamidouche

Cabarat

et al. 2019

IEEE Access

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Scalable high-efficiency video coding (SHVC) is the scalable extension of the high-efficiency video coding (HEVC) standard. SHVC enables spatial, quality, bit-depth, color gamut, and codec scalability. The architecture of the SHVC encoder is based on multiple instances of the HEVC encoder where each instance encodes one video layer. This architecture offers several advantages of being modular and close to the native HEVC coding block scheme. However, the close-loop SHVC architecture requires the complete decoding of the reference lower layer frames to decode a higher quality layer, which considerably increases the complexity of both encoder and decoder processes. In this paper, we propose an end-to-end 4K real-time SHVC solution, including both software encoder and decoder, for video broadcast applications. The SHVC codec relies on low-level optimizations for specific Intel x86 platform and parallel processing to speed up the encoding and decoding processes. The proposed encoder enables real-time processing of 4Kp30 video in 2× spatial scalabilities on the 4 × 10 cores Intel Xeon processor (E5-4627V3) running at 2.6 GHz. In addition, the SHVC decoder enables to decode, respectively, the lower quality layer in full HD (1920 × 1080p30) resolution, an advanced RISC machine (ARM) Neon mobile platform, and the enhancement layer in UHD (3840 × 2160p30), on a fitted laptop, with 4 cores Intel i7 processor running at 2.7 GHz. Finally, experimental results have shown that the proposed solution can reach a high rate-distortion performance close to the reference SHVC reference software model (SHM) with a speedup of 37 and 66 in intra and inter coding configurations.INDEX TERMS Scalable video coding, HEVC, SHVC extension, real time video codecs.

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“…In [28], a 40nm CMOS hardware decoder is introduced that can process 4k videos in real-time. In [17] a more energy efficient 28nm CMOS hardware decoder is presented. Moreover, there are also proposals that focus on a concrete module of the HEVC decoder such as [10,30,18].…”

Section: Related Workmentioning

confidence: 99%

Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors

Rodríguez‐Sánchez

Quintana–Ort́ı

2016

J Real-Time Image Proc

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Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload.The recent HEVC standard, which offers several high-level parallelization strategies, is an important application that can benefit from an implementation tailored for the low-power AMPs present in many current mobile or hand-held devices. In this scenario, we present an architecture-aware implementation of an HEVC decoder that embeds a criticality-aware scheduling strategy tuned for a Samsung Exynos 5422 system-on-chip furnished with an ARM R big.LITTLE TM AMP. The performance and energy efficiency of our solution is further enhanced by exploiting the NEON TM vector engine available in the ARM big.LITTLE architecture. Experimental results expose a 1080p real-time HEVC decoding at 24 frames/sec, and a reduction of energy consumption over 20%.

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A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

Cited by 10 publications

References 7 publications

Low power HEVC software decoder for mobile devices

Low power HEVC software decoder for mobile devices

4K Real Time Software Solution of Scalable HEVC for Broadcast Video Application

Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors

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