A focal plane processor (FPP) for a large array of LWIR photodetectors on a space platform must process large amounts of data, operate reliably in a high-radiation environment. occupy small space, and use little power. This project had the goal of demonstrating that these objectives could be achieved with wafer-scale (XVS) circuit integration on silicon-on-insulator (SOI) wafers. The WS integration technology is Lincoln Laboratory's Restructurable VLSI which uses a laser to form connections and make cuts on two levels of metal. Wafers are fabricated with unconnected circuits and WS interconnect, and after testing the laser is used to alter circuits and to wire together good circuits to achieve customization and defect avoidance. The technology and design tools have been demonstrated through development of six different wafer-scale systems. A technology [called Zone-Melting Recrystallization (ZMR)] for making oxide-isolated wafers had been developed at Lincoln Laboratory and circuits have been fabricated in these wafers. There were four elements in this program: (1) to design a prototype WS FPP. (2) to improve the ZMR process, (3) to develop a CMOS fabrication process in either ZMR or SIMOX SOI wafers, and (4) to fabricate and restructure the WVS FPP. The first three elements were accomplished, but the program was terminated before the wafer-scale circuit was fabricated. This prototype system was designed to handle a 5-column. 64-row scanning detector array in which each detector is sampled every 7 ps. Because cf the relatively low data rate and to minimize wafer-scale interconnect, a serial architecture was used and the system was partitioned into 8 identical processors. To allow fault tolerance 10 processors are provided: an external controller can test them and set multiplexors so that any 8 of the 10 can be used. The processors are hardwired to (1) perform a unique 4-segment offset and gain correction for each detector, (2) delay signals from the 5 columns to time align signals from I target, (3) recognize and reject signals which ma' be ")-corrupted, (4) average 'good' signals, and (5) perform a 4 x 4 filter function and threshold the result. The data correction coefficients, filter kernel, threshold, and-y constant are loaded through a serial bus. Laser restructuring is used to give each circuit on the wafer a unique bus address. Since the circuits were to be built in an experimental process, each replaceable circuit was limited to less than 12,000 transistors which resulted in 5 different circuits. Static CMOS circuitry was used for radiation resistance. All 5 circuits were designed and built in a 3-jm bulk process through the NIOSIS silicon foundry. The circuits operated above the design clock rate of 16 NlHz. and yields were very high in this mature process. With 2 x circuit redundancy for 4 circuits and 1.6 x for the smallest circuit, 5 processors can be fit onto a 45-x 41-mm 2 area on a 3-in wafer so that 2 wafers would be required for the 10-processor system. Each wafer would be packaged in a 2-in squa...
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