Numerical calculations were used to assess the probable microscopic distribution of the electric field along or close to the actual Si-5102 interface of a metal oxide semiconductor (MOS) capacitor biased into accumulation. Silicon wafers were oxidized to 20 nm at 1150°C by rapid thermal oxidation, according to two different thermal recipes in order to yield different Si-5i02 interface roughnesses. After oxide removal, typical atomic force microscopy (AFM) line scans of the silicon surface were exported into the MEDICI program as a description of the Si-5i02 interface in order to calculate the electric field distribution within the oxide layer of a bidimensional MOS capacitor biased into accumulation. This distribution was found to be highly inhomogeneous even for relatively smooth Si-5i02 interfaces, displaying strong local electric field enhancements, the spatial distribution of which will be called electronic roughness in this work. Simple local oxide thinning at the position of the protrusions cannot account for these field enhancements, thus indicating that the shape of the protrusion is dictating the electronic roughness. The electronic roughness could be correlated with electric breakdown characteristics of actual MOS capacitors prepared on these wafers. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Ebd (MV/cm) ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 134.129.182.74 Downloaded on 2015-06-25 to IP

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This paper reports on the efficiency of a less critical chemical cleaning process on the removal of particulates and metal contamination from the silicon surface. Having completed the entire RCA-based cleaning process in either nonfiltered or point-of-use filtered distilled instead of deionized water, a final dip in diluted HF followed by an immersion of the wafer in boiling isopropyl alcohol (IPA) is shown to be effective in reducing particulate levels on its surface without increasing the metal contamination content with regard to previous cleaning steps. It is also shown that early breakdowns of MOS capacitors are predominantly governed by the particulate content on the silicon surface. In addition, it is shown that sulfur can remain on the silicon surface after a dip in diluted HF solution and that after a following hot IPA rinsing, sodium, potassium, calcium, and copper can also be detected on the silicon surface.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 130.160.4.77 Downloaded on 2015-03-30 to IP ABSTRACT Spin coating of a polymer film on a substrate with topography is modeled. Nonnewtonian fluid behavior, solvent diffusivity within coating, and coating leveling are related using this model. The dependence of the coating step height on initial coating concentration, spin speed, feature radial position, and feature dimensions is investigated. For a large feature, the coating profile is dominated by centrifugal force, while for small features the coating profile is dominated by capillary force and the coating is more level. A glassy polymer skin is formed during spinning. The coating profile is then controlled by shrinkage after the skin is formed. The predicted step height is within 10% of that measured experimentally.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 130.160.4.77 Downloaded on 2015-03-30 to IP

The influence of two different thermal annealing cycles on the microroughness of the Si-SiO, interface and on the electrical characteristics of the Si-SiO, system has been investigated. Experiments were performed growing oxides by rapid thermal oxidation @TO) and post-oxidation annealing in N , using a slow cooling ramp recipe (SCRR) or a conventional pulsed thermal annealing recipe (PTAR). Compared to PTAR, SCRR yielded a more severe annealing in N , and slower temperature decay after MO. The thickness of the as-grown oxides was measured by ellipsometry in the whole wafer area. Laser light scattering (us) at a grazing angle and atomic force microscopy (AFM) have been used for measuring the Si-SiO, interface topography after the Si O, removal. LLS was mainly used for large-area scans (micrometric resolution) and AFM for smaii-size areas (atomic 'resolution). The results showed that oxides prepared with SCRR exhibited a smoother Si-SiO, interface at the nanometric scale and protrusions up to 2.5 nm high and up to 100 nm wide ('large protrusions') at a submicrometre scale. On the other hand, the oxides prepared with PTAR resulted in an Si-SiO, interface with protrusions up to 2 nm high and up to 5 nm wide ('sharp protrusions') at the nanometric scale and broad localized regions, sparsely distributed over the wafer area, with high root mean square (RMS) microroughness. By measuring the electrical parameters of a large number of MOS capacitors made with these oxides, we demonstrated evident experimental correlation of the electric breakdown fieid (Ebd), charge to breakdown (Qbd), Si-SiO, interface state density (D,J and AI-SiO, potential barrier height (q40) with surface microroughness and therefore with the thermal annealing cycle in N,. The oxides prepared by SCRR exhibited improved overall electrical parameters as compared to the oxides prepared

An alternative doping process to ion implantation for the production of very shallow p'-n junctions has been investigated. The n-type silicon wafers covered with a boron-doped silicon oxide were submitted to thermal cycles with incoherent light radiation to temperatures between 900 and 1250 "C for times ranging from 20 to 120 S, in order to promote boron in-diffusion. The samples were characterised by sheet resistance measurements combined with sequential layer removal to obtain the carrier concentration-depth profiles. The results show the formation of a boron-rich surface layer above the normal boron solubility levels and a linear dependence of the sheet conductance on diffusion time, which suggests a chemical reaction at the silicon surface is the controlling factor for the boron in-diffusion. Moreover it was demonstrated that defect-free p*-n junctions with a junction depth as shallow as 50 nm are readily obtained.

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The effect of Si/SiO2 interface roughness on SiO2 breakdown characteristics is investigated by means of numerical calculations. It is shown that similar roughness values of the Si/SiO2 interface may yield different breakdown distributions. It is aL~.o shown that severe field enhancement effects may occur at the Si/SiO2 interface for some specific Si/SiO2 interface asperities. A possible correlation between Si/SiO2 interface roughness, oxygen precipitates, and breakdown characteristics is addressed.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 150.135.239.97 Downloaded on 2015-05-31 to IP