In this paper we present methods for generating bounds on interconnection delays in a combinational network having specified timing requirements at its input and output terminals. An automatic placement program which uses wirability as its primary objective could use these delay bounds to generate length or capacitance bounds for interconnection nets as secondary objectives. Thus, unlike previous timing-driven placement algorithms described in the literature, the desired performance of the circuit is guaranteed when a wirable placement meeting these objectives is found. We also provide fast algorithms which maximize the delay range, and hence the margin for error in layout, for various types of timing constraints. * * Ellen J. Yoffa (M'86) received the B.S. and Ph.D. degrees in physics from the Massachusetts Institute of Technology, where her area of study was theoretical solid-state physics. In 1978, she joined the IBM Thomas J. Watson Research Center for postdoctoral work in the Semiconductor Science and Technology Depanment, where she investigated ballistic conduction in semiconductor devices and the physics of the laser annealing process. Since 1980, she has been a member of the research staff in the Computer Science Department and is currently senior manager of the System Design and Verification Department, where she is responsible for managing research in tools for computer-aided design of VLSI chips, including system description and early design tools, logic synthesis, and hardware and software logic simulation. She is a member of the editorial board of lEEE Design and Tesf of Computers. Her research has involved the development of tools for VLSI physical design automation. Dr. Yoffa is a member of Phi Beta Kappa and Sigma Xi.

A number of problems in solid state physics and materials science can be resolved by the evaluation of certain lattice sums (sums over all sites of an infinite perfect lattice of some potential energy function). One classical example, the calculation of lattice sums of circular and spherical harmonics, dates back to the last century, to Lord Rayleigh’s work on computing the effective conductivity of a simple composite. While Lord Rayleigh presented an efficient asymptotic method for two-dimensional problems, he resorted to direct evaluation of the lattice sums in the three-dimensional case. More recent methods, based on Ewald summation, have been developed by Nijboer and De Wette, Schmidt and Lee, and others. In this article, a fast method for evaluating lattice sums which is based on a new renormalization identity is described.

A logic designer today faces a growing number of design requirements and technology restrictions, brought about by increases in circuit density and processor complexity. At the same time, the cost of engineering changes has made the correctness of chip implementations more important, and minimization of circuit count less so. These factors underscore the need for increased automation of logic design. This paper describes an experimental system for synthesizing synchronous combinational logic. It allows a designer to start with a naive implementation produced automatically from a functional specification, evaluate it with respect to these many factors, and incrementally improve this implementation by applying local transformations until it is acceptable for manufacture. The use of simple local transformations in this system ensures correct implementations, isolates technology-specac data, and will allow the total process to be applied to larger, VLSI designs. The system has been used to synthesize masterslice chip implementations from functional specacations, and to remap implemented masterslice chips from one technology to another while preserving their functional behavior. Several tools have been developed at Carnegie-Mellon University to support the early part of the design cycle [ll-141. In one experiment [15] the CMU-DA (Carnegie-Mellon University-Design Automation) system was used to implement the data path portion of a Digital Equipment Corporation (DEC) PDP3/E. It began with a functional Copyright 1981 by International Business Machines Corporation. Copying is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. 272 The title and abstract may be used without further permission in computer-based and other information-service systems. Permission to republish other excerpts should be obtained from the Editor.

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