Functional comparison of logic designs for VLSI circuits

Berman, C.L.; Trevillyan, Louise

doi:10.1109/iccad.1989.76990

Cited by 57 publications

(23 citation statements)

References 7 publications

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“…The case when circuits to be checked for equivalence have compact BDDs under different variable orders was studied in [13]. The most popular method of handling large circuits is based on employing cut points [2] [3]. The idea is to prove functional equivalence of circuits N 1 and N 2 inductively.…”

Section: Ec Of Large Circuitsmentioning

confidence: 99%

On Complexity of Internal and External Equivalence Checking

Goldberg

Gulati

2007

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

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Section: Ec Of Large Circuitsmentioning

confidence: 99%

On Complexity of Internal and External Equivalence Checking

Goldberg

Gulati

2007

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

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“…Our research leverages the success of equivalence checking for logic synthesis [33,5,7], and employs these ideas for equivalence checking for behavioral synthesis.…”

Section: Equivalence Checking For Logic Synthesismentioning

confidence: 99%

“…The major practical reduction technique for combinational equivalence checking is cut-points [5,7]. The main idea is to look for the corresponding points in the two circuits that can be proven to be equivalent; then the equivalent circuits can be cut out of circuits and replaced by new primary symbols.…”

Section: Equivalence Checking For Logic Synthesismentioning

confidence: 99%

Developing a Strategic Policy Choice Framework for Technological Innovation: Case of Chinese Pharmaceuticals

Chan¹

2000

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The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition.However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis into practice.The major research challenge to equivalence checking for behavioral synthesis is the significant semantic gap between ESL and RTL. The semantics of ESL involve untimed, sequential execution; however, the semantics of RTL involve timed, concurrent execution. We propose a sequential equivalence checking (SEC) framework for certifying a behavioral synthesis flow, which exploits information on successive

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“…Structure-based approaches can either use ATPG algorithms [3], or recursive learning [9,10], whereas mixed approaches use structural information, Reduced Ordered Binary Decision Diagrams (ROBDDs) and, in some cases, different forms of learning [6,17]. Approaches that relate and substitute internal circuit nodes can exhibit the false negative problem [2], i.e. declaring two circuits not equivalent when they are in fact equivalent.…”

Section: Introductionmentioning

confidence: 99%