Global flow optimization in automatic logic design

Berman, C.L.; Trevillyan, Louise

doi:10.1109/43.79493

Cited by 30 publications

(18 citation statements)

References 10 publications

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“…2(b), this is implemented as combinational circuit for the example, and . Note that the choice of the original function as a (trivial) cofactor ignores the don't care conditions as given by (3). The fact that the cofactors are not optimized with respect to these don't cares leads to untestable stuck-at faults as indicated.…”

Section: Manipulating Combinational Network By Atpgmentioning

confidence: 99%

“…Even with much recent progress, e.g., [3], [8], [10], [14], [16], [18], [19], [25]- [27], [31], [32], [34], and [38], the size and complexity of today's integrated circuits leave multilevel logic optimization a major challenge in the field of computeraided circuit design. In particular, high-memory requirements represent the dominating limitation for many methods.…”

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confidence: 99%

“…Analyzing implications is crucial for deriving good circuit transformations. In this aspect our method also relates to [3] and [18].…”

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confidence: 99%

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Logic optimization and equivalence checking by implication analysis

Kunz

Stoffel

Menon

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are "good" candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This has already been shown for random pattern testability [11] and low-power consumption [28]. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technologyindependent minimization techniques. For many benchmark circuits, our tool Hannover implication tool based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification. Experimental results show that our optimization-based verification technique works robustly for practical verification problems on industrial designs.

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Section: Manipulating Combinational Network By Atpgmentioning

confidence: 99%

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confidence: 99%

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Logic optimization and equivalence checking by implication analysis

Kunz

Stoffel

Menon

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Various algorithms have been proposed to extract subsets of don't cares (see for example [68,69]). Optimization with don't cares has a close relation to other optimization methods, such as transduction [70], redundancy removal [10] and global flow analysis [71,72]. Techniques based on these methods have been successfully implemented in BooleDozer [73], a synthesis tool from IBM.…”

Section: Chapter 3 Logic Synthesismentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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“…Simultaneous addition and removal of many redundant wires can be obtained with the global flow method [10]. This method uses the concept of mandatory assignments and a graph-theoretic problem formulation to redesign the fan-out branches of a single stem.…”

Section: Introductionmentioning

confidence: 99%