Abstract-This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are "good" candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This has already been shown for random pattern testability [11] and low-power consumption [28]. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technologyindependent minimization techniques. For many benchmark circuits, our tool Hannover implication tool based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification. Experimental results show that our optimization-based verification technique works robustly for practical verification problems on industrial designs.

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It is shown that verifying the timing of a circuit by testing may require tests which can detect the simultaneous presence of more than one path delay fault. We introduce a special class of path delay faults, called primitive faults, whose detection w shown to be necessary and suficient to ensure the temporal correctness of a circuit. Using this result, we develop a synthesis procedure for combinational circuits that can be tested for correctness of timing. Ezperimental data show that such implementations usually require less area than completely delay testable implementations.

A b s t r a c tThe widespread use of field programmable gate arrays (FPGAs) as components in highperformance systems has increased the significance of path delay faults in FPGAs. We present a technique for FPGA path delay fault detection which integrates test insertion with the FPGA placement and routing stages to accomplish testing with low test application time. An accurate static timing analyzer is used to identify critical paths and built-in selftest (BIST) hardware is inserted using a placement and routing tool. Initial experimental results show that testing is accomplished with low test application time for several benchmark designs.