Logic Synthesis Through Local Transformations

Abstract

A logic designer today faces a growing number of design requirements and technology restrictions, brought about by increases in circuit density and processor complexity. At the same time, the cost of engineering changes has made the correctness of chip implementations more important, and minimization of circuit count less so. These factors underscore the need for increased automation of logic design. This paper describes an experimental system for synthesizing synchronous combinational logic. It allows a designer to start with a naive implementation produced automatically from a functional specification, evaluate it with respect to these many factors, and incrementally improve this implementation by applying local transformations until it is acceptable for manufacture. The use of simple local transformations in this system ensures correct implementations, isolates technology-specac data, and will allow the total process to be applied to larger, VLSI designs. The system has been used to synthesize masterslice chip implementations from functional specacations, and to remap implemented masterslice chips from one technology to another while preserving their functional behavior. Several tools have been developed at Carnegie-Mellon University to support the early part of the design cycle [ll-141. In one experiment [15] the CMU-DA (Carnegie-Mellon University-Design Automation) system was used to implement the data path portion of a Digital Equipment Corporation (DEC) PDP3/E. It began with a functional Copyright 1981 by International Business Machines Corporation. Copying is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. 272 The title and abstract may be used without further permission in computer-based and other information-service systems. Permission to republish other excerpts should be obtained from the Editor.

Novel Approach To Synthesis of Logic Circuits Based on Multifunctional Components

“…These cases are mostly focused on variations of the truth table forms together with disjunctive/conjunctive representation. For the sake of completeness it is important to note that synthesis and minimization techniques in digital circuit domain are based extensively on multi-level representations as well [18][19][20], especially due to a reasonable compromise between compact representation and efficient manipulation. Probably one of the most illustrative examples here is tied with decision diagrams or, to be precise, BDD (Binary Decision Diagrams) as the widely adopted scheme in various situations.…”

Integrated logic synthesis using simulated annealing

“…Such transformations have limited optimization capability since they are local in nature, and do not have a global view on the design. Examples of systems based on this approach are LSS [2] and LORES/EX [67].…”

“…Let p (2) i j be the probability that if the Markovian random variable is in state s i at time t, then it is in state s j at time t + 2. We call this a two-step transition probability.…”

“…Thus if the matrix P (2) is defined as the matrix whose (i, j) element is p (2) i j , then the (i, j) element in P 2 is equal to the (i, j) element in P 2 . This leads to the identity P (2) = P 2 .…”

“…Traditional logic synthesis is partitioned into multiple phases, such as technology independent synthesis, technology mapping, and timing optimization [2,3,4]. During the technology independent phase, simple literal count is applied as the primary quality metric for defining the global structure of the circuit implementation.…”