-This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed GatedClock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2ns keeping timing constraints for enable-logic parts.
This paper describes the expert system which automatically generates the logic circuit composed of elements registered in the cell library, receiving the functional description at the register transfer level of the hardware as the input. The features of the system are that it includes the dedicated circuit data structure, the rule description language, and the corresponding processing system, which can generate a high‐quality large‐scale circuit in a short processing time.
In other words, by introducing the technology‐independent functional elements into the data structure, the circuit can be generated by effectively utilizing the high‐level functional library elements. By including the mechanism for the local transformation into the system and by other sophistications, a practical processing speed is realized. The knowledge depending on the library and the user, is formulated into rules. This is useful in providing the system with flexibility. The system has already been applied to the development of more than 30 kinds of practical products. Using a large‐scale computer with 15 MIPS, a circuit with several thousands of gates can be generated automatically in 4 to 12 min.
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