Generation of performance constraints for layout

Abstract

In this paper we present methods for generating bounds on interconnection delays in a combinational network having specified timing requirements at its input and output terminals. An automatic placement program which uses wirability as its primary objective could use these delay bounds to generate length or capacitance bounds for interconnection nets as secondary objectives. Thus, unlike previous timing-driven placement algorithms described in the literature, the desired performance of the circuit is guaranteed when a wirable placement meeting these objectives is found. We also provide fast algorithms which maximize the delay range, and hence the margin for error in layout, for various types of timing constraints. * * Ellen J. Yoffa (M'86) received the B.S. and Ph.D. degrees in physics from the Massachusetts Institute of Technology, where her area of study was theoretical solid-state physics. In 1978, she joined the IBM Thomas J. Watson Research Center for postdoctoral work in the Semiconductor Science and Technology Depanment, where she investigated ballistic conduction in semiconductor devices and the physics of the laser annealing process. Since 1980, she has been a member of the research staff in the Computer Science Department and is currently senior manager of the System Design and Verification Department, where she is responsible for managing research in tools for computer-aided design of VLSI chips, including system description and early design tools, logic synthesis, and hardware and software logic simulation. She is a member of the editorial board of lEEE Design and Tesf of Computers. Her research has involved the development of tools for VLSI physical design automation. Dr. Yoffa is a member of Phi Beta Kappa and Sigma Xi.

A Unified Theory of Timing Budget Management

“…Hence, maximizing the total budget can lead to further optimization in the area. In our previous work [11], we theoretically and empirically showed that optimal maximum budgeting outperforms ZSA [23] in reducing the design size. Maximum budgeting reduced the design size by more than 10% on average compared to ZSA algorithm.…”

“…Almost all of the techniques employed in these works are suboptimal heuristics such as Zero Slack Algorithm [23] and MISA [2]. In our previous work [11], we solved the problem of integral delay budgeting through LP relaxation.…”

Minimum-area sequential budgeting for FPGA

“…Timing-driven placement is a technique to improve a circuit's speed. Several approaches for timing-driven placement have been proposed, one of which involves net budgeting [5][2] [9]. For an expected clock period defined by a user, budgeting converts the path timing constraints into timing (or length) upper bounds for nets.…”

“…Most of the previous works on delay budgeting have been focused on optimizing combinational circuits [5] [2]. For sequential circuits, it is usually assumed that FFs are at fixed positions, and they are treated like primary inputs (PIs) and outputs (POs).…”

Efficient implementation selection via time budgeting: complexity analysis and leakage optimization case study

“…The majority of previous work have used heuristics based on Zero Slack Algorithm (ZSA) [11] to assign timing constraints to design components. Previously, we presented optimal algorithms for integral time budgeting on a DAG [6,13] and showed their superiority over ZSA.…”