Minimum-area sequential budgeting for FPGA

Abstract

The constraint-based approach to timing-driven placement requires delay budgeting to define the delay upper bounds for nets. While most of the previous delay-budgeting works have been focused on optimizing combinational circuits, the work in [9] introduces sequential budgeting, which combines budgeting and retiming to optimize sequential circuits better. However, the formulation in [9] does not consider flip-flop (FF) minimization, which is important in practical applications. Here, we propose a new sequential budgeting algorithm, C-SBGT, that not only controls the FF count, but also can be solved more efficiently compared to [9]. Our formulation has fewer constraints than [9] and the procedure to realize retiming is also simpler. Our experiments show that our new min-area sequential budgeting algorithm produces a good trade-off between the area and budgeting optimization goals, as well as improving the timing of previous sequential budgeting method by 12%.