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This papers presents new results on silicon I-MOS devices, (where the source and the drain are doped of opposite type) obtained by an adaptation of a conventional CMOS process. Fabricated devices are fully functional down to 55nm of gate length, but the influence of the gate becomes strongly reduced for shorter devices due to technological limitations. Nevertheless, the smallest device, with a 17nm gate length and with an avalanche threshold of 5.3V, is reported. The corresponding output current-voltage features an equivalent resistance as low as 66Ω.µm. For all devices, the maximum current is only limited by the contacts destruction, positioning the measured value of 4700µA/µm among the highest ever reported for a MOS device. In addition, it is shown that the extrapolated I on /I off figure of merit is close to complying with the specifications imposed to the HP flavor of the ITRS'05 roadmap.