On the Limitations of Silicon for I-MOS Integration

Savio, Andrea; Monfray, S.; Charbuillet, C.; Skotnicki, T.

doi:10.1109/ted.2009.2015163

Cited by 34 publications

(10 citation statements)

References 15 publications

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“…[10] For most electronics, the operating voltage is generally 1.5$12.0 V (i.e., a few dry batteries or button batteries). For example, the silicon impact ionization metal-oxide-semiconductor (I-MOS) fieldeffect transistors require a supply voltage of $5.5 V. [11,12] Concerning the conventional single junction solar cells, the open-circuit voltage (V OC ) depends on the bandgap of the semiconductor material and the intensity of sunlight. [13] Taking silicon solar cell as an example, the V OC is generally less than 0.75 V under a standard air mass (AM) 1.5G spectrum (1000 W m À2 ).…”

Section: Introductionmentioning

confidence: 99%

Realization of High‐Voltage Output on Monolithic Silicon Solar Cells in Series for Self‐Powered Systems

Lin

Chen

et al. 2022

Solar RRL

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Crystalline silicon solar cells dominate the photovoltaic market nowadays. However, they are rarely used in self‐powered systems (with an operating voltage of 1.5∼12.0 V) mainly because of the low integration of silicon solar cell modules, which need slicing and then series connection. Herein, a series‐interconnected solar cell which can be prepared on a monolithic silicon wafer, with the capability to output high voltage by controlling the number of sub‐cells, is proposed. Further, based on a technology computer aided design (TCAD) numerical simulation, an in‐depth analysis of an unconventional non‐shunt resistance type of leakage mechanism under electric and light injection which has not been reported before is proposed and performed, finding that the leakage current can be divided into three stages that are closely related to the variation in the conductivity (resistance) of the transition region (TR) under injection conditions. Then, several targeted methods especially an unusual method of increasing the recombination to constrain the rise in conductivity in TR are proposed to improve its efficiency by suppressing leakage current at different stages. Finally, simulation reveals that the proposed monolithic on‐chip solar micromodules enable not only high voltage but also high efficiency (≥24.0%), which well meets the requirements of self‐powered systems at low cost.

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Section: Introductionmentioning

confidence: 99%

Realization of High‐Voltage Output on Monolithic Silicon Solar Cells in Series for Self‐Powered Systems

Lin

Chen

et al. 2022

Solar RRL

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“…However, this lateral IMOS needs a high supply voltage (V DS ) and suffer from degradation caused by hot carrier effects. Hence, causing reliability issues [6][7].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Saad

Hamzah

Seng

et al. 2013

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The comparison between VESIMOS and VESIMOS-DP was done to show the advantages of incorporating dielectric pocket (DP) to the performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to the delta p+ (δp+) triangular potential barrier. Thus, increased amount of gate voltage needed to overcome those barriers and allows the electrons to flow from source to drain. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer. Hence, the incorporation of DP into VESIMOS has enhanced its performance and presents elevated characteristics for nano-electronics device.

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“…However, this lateral IMOS needs a high supply voltage and suffers from reliability problems due to hot carrier effect [9][10][11]. To counter this effect, vertical IMOS has been introduce and investigated [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

Saad

Zuhir

Seng

et al. 2013

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics

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The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. It is notable that for body doping concentration above 10 20 , the S values keep increasing which is not recommended as the switching speed getting higher distracting performance of the device. An improved stability of threshold voltage, V TH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage for VESIMOS-DP with high body doping concentration. VESIMOS-DP with low body doping concentration suffers PBT effect that prevents the device from being able to switch off. Hence, high body doping concentrations are imperative for obtaining better device characteristics and ensure the device works in II mode.

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On the Limitations of Silicon for I-MOS Integration

Cited by 34 publications

References 15 publications

Realization of High‐Voltage Output on Monolithic Silicon Solar Cells in Series for Self‐Powered Systems

Realization of High‐Voltage Output on Monolithic Silicon Solar Cells in Series for Self‐Powered Systems

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

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