A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. The 20-MHz sixth-order Bessel filter and second-order equalizer operate from 5 V, and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2-VP-P differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mb/s, and is built in a 1.5-~m, 4-GHz BiCMOS technology.
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