A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels

Abstract

A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. The 20-MHz sixth-order Bessel filter and second-order equalizer operate from 5 V, and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2-VP-P differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mb/s, and is built in a 1.5-~m, 4-GHz BiCMOS technology.

A “Divide and Conquer” Technique for Implementing Wide Dynamic Range Continuous-Time Filters

“…13(b) where we plot the error between the amplitudes responses with filter B as the reference ( output only). The amplitude error is seen to be smaller than 0.2 dB across the entire passband (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19). Fig.…”

“…This allowed us to perform automatic tuning of the center frequency by simply "locking" a replica to a stable external reference resistance [11] and using the resulting bias voltage to bias the transconductors of the filters. No tuning was necessary because of the large dc gain and good high-fre quency behavior of the transconductors used in the design (see the next section).…”

A Discrete-Time Downsampling FIR Filter for Windowed Integration Samplers

“…In addition to sampling capacitor C s , it has parasitic capacitance C par (Figure 10(a)), which is the result of parasitic diodes, overlaps, crossings, strays and fringing effects [7]. The voltage dependence of the parasitic capacitance makes the response sensitive to power supply variations and degrades the distortion performance [7,8]. Also, the finite output impedance of the Gm stage gets modulated by the swing of the voltage signal at its output.…”

“…The basic passive integrator consisting of just an integrator driving a capacitor has some certain disadvantages. In addition to sampling capacitor C s , it has parasitic capacitance C par (Figure 10(a)), which is the result of parasitic diodes, overlaps, crossings, strays and fringing effects [7]. The voltage dependence of the parasitic capacitance makes the response sensitive to power supply variations and degrades the distortion performance [7,8].…”

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

“…A slightly negative output conductance will not cause filter instability, however, because of negative feedback, loops inherently present in the biquadratic loop . Regardless, the most popular choice is the inclusion of a cascode stage (simple [9], [10], active [11], [12], folded [13], [14], telescopic [15], [16]) or a cascaded output stage such as the -op-amp [17]- [21] to improve the integrator dc gain, and attempt to cancel the associated parasitics directly.…”