A family of differential NMOS analog circuits for a PCM codec filter chip

Senderowicz, D.; Dreyer, Stefan; Huggins, J.H.; Rahim, C.F.; Laber, C.A.

doi:10.1109/jssc.1982.1051855

Cited by 122 publications

(22 citation statements)

References 6 publications

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“…The input stage and the output stage have separate common mode feedback loops for two reasons: first, it is easier to achieve fast and accurate CMFB without a fear of instability with separate loops and, second, the firststage CMFB is used to charge the level shift capacitor, which is not possible with a single loop since the signal path between the stages is broken during charging. Both the CMFB circuits are realized with standard SC circuits [179]. …”

Section: Two-stage Bicmos Opampmentioning

confidence: 99%

“…Since a series switch cannot be put in the output of the opamp, the traditional SC common mode feedback circuit [179] cannot be directly utilized in SO circuits. The circuit shown in Figure 10.10 performs the common mode sensing with a capacitive divider consisting of capacitors C P and C M , which are permanently connected to the opamp outputs.…”

Section: Fully Differential Switchable Opampmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Two-stage Bicmos Opampmentioning

confidence: 99%

Section: Fully Differential Switchable Opampmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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“…The current through Q 1 and Q 2 is set to a constant value of I 2 . This results in a dc bias current of I 1 -I 2 through Q 3 and Q 4 which is consequently mirrored to Q 5 and Q 6 . Since a constant current of I 2 is forced through Q 1 and Q 2, the individual gate-source voltages of these transistors remain fixed.…”

Section: Filter Designmentioning

confidence: 99%

“…(5) and Eq. (6). If the variation of a quantity is denoted by the characteristic , then the sensitivity of the center frequency, , is given by a Taylor series expansion with respect to the dependent variables where second-order and higher-order terms are neglected (i.e.,…”

Section: Filter Designmentioning

confidence: 99%

A low-voltage CMOS filter for hearing aids using dynamic gate biasing

Pylarinos

Wong

Phang

Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)

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-In this paper we discuss the design of a low-voltage (1.5V), continuous-time, biquadratic CMOS filter based on Dynamic Gate Biasing (DGB). We begin by discussing the filter's structure and its tuning mechanism. The filter uses transconductance-C cells and implements low-pass, bandpass and highpass transfer functions. The transconductances are tuned using the gate voltages of MOSFETs operating in the triode region. We review the principle of DGB, and discuss the design of the charge pump based on the filter's performance and tunability requirements. Circuit details of the filter elements and the charge pump are presented along with SPICE simulation results of the overall filter.

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“…The two differential output voltages are averaged (V CM Resistor-averaged circuit Suffering from clock-induced noise, switchedcapacitor common-mode feedback circuits are suitable only for sampled-data circuits [1] [2]. Common-mode feedback circuits implemented by differential-difference amplifiers (DDA) use four identical transistors to average and compare the common-mode voltages [3]- [6].…”

Section: Introductionmentioning

confidence: 99%

A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application

Luh

Choma

Draper³

1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.9

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A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to minimize the offset of the common-mode voltage. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. Simulation and testing results show the superior performance of this circuit. It is proven to be an ideal common-mode feedback circuit for systems which require an accurate and stable commonmode voltage. This circuit has been implemented in a continuous-time switched-current modulator with a 2m CMOS process. With a 50MHz clock, the modulator has achieved a 60dB dynamic range in a 1MHz bandwidth.

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A family of differential NMOS analog circuits for a PCM codec filter chip

Cited by 122 publications

References 6 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A low-voltage CMOS filter for hearing aids using dynamic gate biasing

A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application

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