Abstmct-We propose and analyze a recursive modular arcbitecture for implementing a large-scale multiwt output buffered ATM switch (MOBAS). A multicast bmkout principle!, an extension of the generdhd knockout prieiple, is applifd in constructing the MOBAS in order to reduce the hardware complexity (e.g., the number of switch elements and intetconnedon wires) by almost one order of magnitude. In our proposed switch architecture, four major functions of designing a multicast switch: cell replication, cell routing, cell contention qmlution, and cell address@, are all performed distributhdy 80 that a large switch size is achievable. The architecture of the MOfBAS has a regular and uniform structure and, thus, has the advantages ok 1) easy expansion due to the modular structure, 2) high integration density for VLSI implementation, 3) relaxed synchronization for data and dock signals, and 4) building the cater switch fabric (i.e., the multicast grouping network) with two-stage structure of the mdtkast outpu (MOBAS) is described. The p e r f ' e cell loss probability is analyzed, and the nusrerfes1 results technology and tested to operate correctly.
In mission-critical applications such as vehicular networks, distributed robotics, and other cyber-physical systems, the requirements for latency are more stringent than traditional applications. Among them, autonomous V2V communication is a rapidly emerging domain of applications with a few milliseconds' latency requirements. Today's systems utilizing 802.11p or LTE-direct standards are not primarily designed for ultra-low latency. Because the medium access function contributes to a significant portion of the total latency, it is necessary to modify Layer2 in order to solve the problem. Focusing on MAC layer, we developed a scalable and latency-guaranteed MAC by devising Autonomous TDMA (ATDMA) in which autonomous joining/leaving is allowed without scheduling by coordinator. We also evaluated the performance of the algorithm by comparing with the WAVE protocol.
This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channelgrouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a twodimensional array (32 2 32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 m CMOS technology and tested to operate correctly at 240 MHz.
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