Effect of Flow Aggregation on the Maximum End-to-End Delay

Joung, Jinoo; Choe, Byeong-Seog; Jeong, Hongkyu; Ryu, Hyunsurk

doi:10.1007/11847366_44

Cited by 4 publications

(4 citation statements)

References 9 publications

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“…also holds because of (11). We can now calculate the delay of packets in i D p at the node D. The delay of i D p is bounded by (13), where ρ i , L i , and Θ nw−DRR i can be easily obtained by letting i D p be the aggregate of all the flows traverse from the input port p to the output port under observation at the node D. The maximum burst of i D p , σ p , can be obtained similarly with (14).…”

Section: Properties Of the Nw-drrmentioning

confidence: 94%

“…In an SP scheduler, among the packets queued, the packet with the highest priority is selected to be served. It is shown that the strict priority scheduler is also an LR server [11] for a flow, but its latency is a function of the sum of all the other flows' maximum burst sizes as…”

Section: Alternatives To the Intservmentioning

confidence: 99%

“…which is the inequality for the amount of work of a regulator with maximum burst size ϕ i + L i , or an arrival curve of a flow {ρ i , ϕ i + L i } where ϕ i + L i is the max burst size. As the next step, we will introduce a modified DRR that satisfies the two conditions given above, and show that it indeed works as a regulator with inequality (11). Consider a DRR scheduler that is modified to work with the following algorithm.…”

Section: Drr Scheduler As a Regulatormentioning

confidence: 99%

“…There has been a tremendous amount of research activities regarding the end-to-end delay bound in large scale networks, since early 1990s [3][4][5][6][7][8][9][10][11]. While various approaches for such requirements have their pros and cons, meeting delay requirement and implementation simplicity have been incompatible with one another so far.…”

Section: Introductionmentioning

confidence: 99%

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Regulating Scheduler (RSC): A Novel Solution for IEEE 802.1 Time Sensitive Network (TSN)

Joung

2019

Electronics

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Emerging applications such as industrial automation, in-vehicle, professional audio-video, and wide area electrical utility networks require strict bounds on the end-to-end network delay. Solutions so far to such a requirement are either impractical or ineffective. Flow based schedulers suggested in a traditional integrated services (IntServ) framework are O(N) or O(log N), where N is the number of flows in the scheduler, which can grow to tens of thousands in a core router. Due to such complexity, class-based schedulers are adopted in real deployments. The class-based systems, however, cannot provide bounded delays in networks with cycle, since the maximum burst grows infinitely along the cycled path. Attaching a regulator in front of a scheduler to limit the maximum burst is considered as a viable solution. International standards, such as IEEE 802.1 time sensitive network (TSN) and IETF deterministic network (DetNet) are adopting this approach as a standard. The regulator in TSN and DetNet, however, requires flow state information, therefore contradicts to the simple class-based schedulers. This paper suggests non-work conserving fair schedulers, called ‘regulating schedulers’ (RSC), which function as a regulator and a scheduler at the same time. A deficit round-robin (DRR) based RSC, called nw-DRR, is devised and proved to be both a fair scheduler and a regulator. Despite the lower complexity, the input port-based nw-DRR is shown to perform better than the current TSN approach, and to bind the end-to-end delay within a few milliseconds in realistic network scenarios.

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Section: Properties Of the Nw-drrmentioning

confidence: 94%

Section: Alternatives To the Intservmentioning

confidence: 99%

Section: Drr Scheduler As a Regulatormentioning

confidence: 99%