Design and implementation of Abacus switch: a scalable multicast ATM switch

SUMMARYThis paper presents the design and implementation of a new scalable cell-based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non-uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self-routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0:18 mm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing.

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Architecture design, performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Wu¹,

Li²

2008

Int J Communication

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SUMMARYModern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high-speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst-case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer-sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer-sharing scheme by both a numerical model and extensive simulations under uniform and non-uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 m CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high-speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers.

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Design and implementation of Abacus switch: a scalable multicast ATM switch

Cited by 31 publications

References 24 publications

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Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

Architecture design, performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

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