A model of Banyan networks is developed to account for their operational as well as topological characteristics. The model incorporates a description of the states of individual switching nodes and explicitly captures the interconnection patterns between stages. Accordingly, the performance of a network can be evaluated via an iterative procedure. Using the model, we analyzed one class of nonuniform traffic pattern referred to as “point-to-point” traffic that has particular significance to mixed voice, data, and video applications. The results obtained indicate that even a single dedicated channel (with point-to-point traffic) can significantly limit the throughput of the background uniform traffic. The paper concludes with several switch design strategies for switching point-to-point traffic using a self-routing switching network.
SUMMARYModern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high-speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst-case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer-sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer-sharing scheme by both a numerical model and extensive simulations under uniform and non-uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 m CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high-speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers.
The ability to emulate circuit switched signals (e.g. DS1 and DS3 rates) in a broadband packet network permits maximum flexibility for the deployment of broadband packet technology in the public switching network. In particular, as the network evolves from circuit switching to packet switching, both packet and circuit facilities can coexist in such a way that a digital signal may be routed over the appropriate combination of mixed packet and circuit networks to reach its destination. The approach eliminates the need to maintain a packet network as an overlay over the existing network and enables step-by-step introduction of packet switching equipment for upgrading individual transmission and switching components. To show the feasibility of this new networking approach, this paper presents our initial estimates of performance goals and design considerations for synchronous circuit emulation in a broadband network. Based on this study, it appears that the most stringent performance constraint is derived from the synchronization requirement of the emulated circuit signal. Mechanisms for limiting packet losses and delay jitter are identified as two necessary ingredients for emulating circuits in a broadband packet network. Finally, we outline the design of a 2-stage time-space switch to demonstrate the feasibility of circuit emulations.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.