Design and implementation of Abacus switch: a scalable multicast ATM switch

IEEE International Conference on Computer Systems and Applications, 2006.

2006

Abstract-This paper presents the architecture design as well as the performance analysis of a new cell-based multicast switch for broadband communications. Using distributed control and a modular design, the Balanced Gamma (BG) switch features a high performance for unicast, multicast and combined traffic under both random and bursty conditions. Although it has buffers on input and output ports, the multicast BG switch follows predominantly an output-buffered architecture. The performance is studied under uniform and non-uniform multicast traffic in terms of cell loss ratio and cell delay. The results are compared with those from an ideal pure output-buffered multicast switch to demonstrate how close its performance is to that of the ideal but impractical switch. Comparisons with other published switches reveals the superior of the BG switch and the tradeoffs between complexity and performance in a packet switch design. It is shown that the multicast BG switch achieves a performance close to the ideal switch while keeping hardware complexity reasonable.

Section: A Approaches To Construct Multicast Switchmentioning

confidence: 99%

Section: B Justification For Buffering Choicesmentioning

confidence: 99%

Section: B Performance Comparison With Other Switchesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Architecture and Performance Analysis of the Multicast Balanced Gamma Switch for Broadband Communications1

IEEE International Conference on Computer Systems and Applications, 2006.

2006

“…Many possible multicast switch architectures have been explored since the late 1980s, such as the PINIUM switch [1], the ABACUS switch [2], and the input-queued (virtual output queued) switch [3]. Due to the many desirable features such as self-routing, distributed control, modularity, constant delay for all input-output pairs and suitability for VLSI implementation, multistage interconnection network (MIN) design has become an attractive solution for broadband switch architecture.…”

Section: Introductionmentioning

confidence: 99%

Performance Modelling of the Multicast Balanced Gamma Switch

2006 IEEE International Conference on Communications

2006

Abstract-This paper presents an analytical model for the performance analysis of a new cell-based multicast switch for broadband communications. Using distributed control and a modular design, the Balanced Gamma switch features a high performance for unicast, multicast and combined traffic under both random and bursty conditions. Although it has buffers on input and output ports, the multicast BG switch follows predominantly an output-buffered architecture. The analytical model follows the three phase switching operation. The performance is evaluated under multicast random traffic in terms of cell loss ratio and cell delay. Performance under bursty traffic is studied through simulation and the results are compared to those of an ideal pure output-buffered multicast switch.

Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

2006

Int J Communication

SUMMARYThis paper presents the design and implementation of a new scalable cell-based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non-uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self-routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0:18 mm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing.