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A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.

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P+IPW N+/NW -l r l r i 0 . 8 . 0 0 . ! f . *. 0 t -. " ' . ! ' . A 180 nm generation logic technology has been developed with high performance 140 nm L G A~ transistors, six layers of aluminum interconnects and low-& SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power.The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiOz inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 pm2 6-T cell size have been built on this technology as a yield and reliability test vehicle.

The surface chemistry of n-type Si electrodes that had been etched, exposed to electrolyte, and electrochemically cycled has been probed using high-resolution X-ray photoelectron spectroscopy (XPS). n-Si surfaces etched in hydrofluoric acid-ethanol solutions (in air or N, ambients) displayed spectra in the Si 2p region that were free of detectable substrate oxide signals (15 X lo-" mol cm-, SO,; equivalent to 14% of a monolayer). Exposure of HF-C2H50H etched or of 49% HF(aq) etched n-Si surfaces to an electrolyte solution containing CH30H, dimethylferrocene (Me2Fc), and dimethylferricenium (Me2Fc+) generated very low levels, 1 ( 2 f 1) X mol cm-2 of silicon suboxides. Only sub-monolayer levels of SiO,, (4 f 2) X mol cm-2, were detected after electrochemical cycling of illuminated n-Si anodes in contact with CH30H-Me2Fc+/0 electrolytes. Even n-Si photoanodes maintained at short circuit with the CH30H-Me2Fc+/0 electrolyte for substantial periods (> 1000 C cm-, anodic charge passed) formed less than a single monolayer of strained Si02 at the silicon surface. Deliberate anodization of the Si surface in these electrolyte solutions yielded controlled amounts of thicker (8-10 A) Si02 overlayers; these overlayers provided a useful oxide for the formation of high-performance metal-insulatorsemiconductor device structures. These studies demonstrate that HF-C2H50H-or HF(aq)-etched n-Si surfaces are remarkably resistant to oxide formation during photoelectrochemical cycling in CH30H-based electrolytes, and that the outstanding photoelectrochemical Z-Vproperties of the n-Si/CH30H-Me2Fc+/0 junction are not a result of formation of passivating oxide overlayers on the Si surface.