A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

Tyagi, S.; Alavi, Morteza S.; Bigwood, R.; Bramblett, T.; Brandenburg, J.; Chen, W.; Crew, B.; Hussein, Makarem A.; Jacob, Peter; Kenyon, C.; Lo, Chieh-Ting; McIntyre, B.; Ma, Zhuxuan; Moon, Pyung; Nguyen, P.; Rumaner, L.; Schweinfurth, R. A.; Sivakumar, S.; Stettler, M.; Thompson, Scott E.; Tufts, Bruce J.; Xu, Jingwei; Yang, Shiau-Ru; Bohr, M.

doi:10.1109/iedm.2000.904383

Cited by 106 publications

(45 citation statements)

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“…This is achieved by using low devices in the critical sparse-tree and high devices on the noncritical sum-generator paths. The 10 differential in leakage currents between high and low devices [4] results in an overall 56% reduction in leakage energy consumption without impacting performance ( Table I). Note that highallocation was performed on an initial all-low-design without transistor resizing.…”

Section: A Dualdesignmentioning

confidence: 99%

“…Thus, the output of the compressor array is a pair of 32-bit numbers that represent the carry-save format of the effective address. This phase of address computation includes the latch data-to-delay, shifter delay, 3 : 2 compressor delay and setup time at the adder core inputs and takes 98 ps in a 1.2-V 130-nm technology [4]. During this phase, the adder core will be in the precharge state.…”

Section: Agu Architecturementioning

confidence: 99%

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A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

Mathew

Anders

Krishnamurthy

et al. 2003

IEEE J. Solid-State Circuits

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Abstract-This paper describes a 32-bit address generation unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-T semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.Index Terms-Address generation unit (AGU), high-performance adders, semidynamic design, sparse-tree adder.

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Section: A Dualdesignmentioning

confidence: 99%

Section: Agu Architecturementioning

confidence: 99%

A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

Mathew

Anders

Krishnamurthy

et al. 2003

IEEE J. Solid-State Circuits

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show abstract

“…other known techniques to reduce leakage during standby mode but in this paper we focus on runtime leakage reduction which is a more difficult and pressing problem. Currently dual-V th is the only practical approach to achieving substantial runtime leakage reduction [9].…”

Section: Overview Of Encodingmentioning

confidence: 99%

Leakage-and crosstalk-aware bus encoding for total power reduction

Deogun

Rao

Sylvester

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

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Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

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“…All simulations are performed at a temperature of 100C. A typical global metal layer for a 0.13µm technology node [9] is used for routing the bus, with a minimum pitch of 1.2µm (Fig. 9).…”

Section: Energy/current-delay Comparisonsmentioning

confidence: 99%

Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses

Kaul

Sylvester

Anders

et al. 2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single cycle operation at 1GHz, with delay and energy overhead of the encoding included. For throughput constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths.

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A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

Cited by 106 publications

References 0 publications

A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

Leakage-and crosstalk-aware bus encoding for total power reduction

Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses

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