Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses

Abstract

We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single cycle operation at 1GHz, with delay and energy overhead of the encoding included. For throughput constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths.

A Data Capturing Method for Buses on Chip

“…Additional ones exist for minimizing coupled switchings on lines [29], [37], [38], reducing transitions on lines [5], minimizing dynamic [39], static [6], peak [36] and leakage power [7]. Existing codes for crosstalk impact minimization like the Dual Rail (DR) and the Modified Dual Rail (MDR) codes in [24], [25] require more than 100% wire overhead.…”

High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS

“…The transition-encoded dynamic bus technique [4] employs temporal encoding on a dynamic bus to achieve higher performance than static buses while still retaining the energy-profile of static buses. Lowlatency spatial encoding circuit designs [5] can achieve peak power and current reductions in buses at a given performance target by limiting the number of simultaneously switching wires.…”