Electrothermal modeling of silicon carbide (SiC) power devices is frequently performed to estimate the device temperature in operation, typically assuming a constant thermal conductivity and/or heat capacity of the SiC material. Whether and by how much the accuracy of the resulting device temperature prediction under these assumptions is compromised has not been investigated so far. Focusing on high-temperature operating conditions as found under short circuit (SC), this paper presents a comprehensive analysis of thermal material properties determining the temperature distribution inside SiC power MOSFETs. Using a calibrated technology computer-aided design (TCAD) electrothermal model, it is demonstrated that the temperature prediction of SiC power devices under SC operation when neglecting either the top metallization or the temperature dependence of the heat capacity is inaccurate by as high as 25%. The presented analysis enables to optimize compact electrothermal models in terms of accuracy and computational time, which can be used to assess the maximum temperature of SiC power MOSFETs in both discrete packages and multichip power modules exposed to fast thermal transients. A onedimensional thermal network of a SiC power MOSFET is proposed based on the thermal material properties, the size of the active area of the device, and its thickness. Index Terms-Electrothermal (ET) modeling, short circuit (SC), silicon carbide (SiC), TCAD, thermal conductivity. I. INTRODUCTIONW ITH the ever-increasing requirements for energy saving, the adoption of silicon carbide (SiC) power transistors has been following a growing trend across different power electronic (PE) applications, including electrical vehicles (EVs), EV charging infrastructure, power factor correction, power supply, photovoltaics, uninterruptible power supplies, motor drives, wind, and rail [1]. Increasing the acceptance of the emerging SiC technology in the field of high-frequency, high-temperature, and/or high-power applications needs to be supported by a comprehensive understanding of SiC material properties and their influence on the system performance. Nowadays, multiphysics modeling tools based on the underlying physics of the SiC material are widely employed both in academia and industry to

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Optimized low-inductive layouting of the package interconnections and external PCBs and bus-bars are necessary to benefit from Silicon Carbide (SiC) power devices, which allow inherently very fast switching transitions. In this paper, a comprehensive modeling procedure for highly accurate virtual dynamic characterization of discrete SiC power devices is described taking into account the 3D geometry of the internal and external interconnections of package as input. The modeling requirements are discussed on an example of a commercial 1.2 kV, 80 mΩ SiC Power MOSFET in a standard TO-247 package (Cree C2M0080120D). The software tools, Simplorer, Saber, Q3D and LTSpice, commonly used for modeling and simulation of power modules, are evaluated with respect to their modeling capabilities for SiC devices.

New generations of silicon carbide (SiC) based MOSFETs are commercially available from manufacturers featuring smaller chip size with higher power density demonstrating performance improvement compared to their previous generation counterparts. As the size of the chip is small, the volume available to dissipate energy during short-circuit (SC) like conditions is reduced, leading to increased self-heating of the device. Therefore, the short circuit withstand time (SCWT) is reduced. As a reliability aspect, ruggedness to extreme operating conditions like SC needs to be analyzed for these devices, to improve the design or to design better detection and protection circuits for these MOSFETs when used in specific SC vulnerable applications. In this work, the new third generation 1.2 kV SiC MOSFET from Wolfspeed in a TO-247-4 pin package having a smaller chip size is measured for SC ruggedness. The causes for device failure under different DC-link voltages, gate bias voltages, SC pulse durations and self-heating behavior are analyzed based on the destructive SC tests performed. The device is measured to have an SCWT of 2 µs at a DC-link voltage of 800 V compared to SCWT of 4.5 µs for the second generation 1.2 kV devices with larger chip size and TO-247-3 pin package. The presence of the Kelvin source contact demonstrates higher peak SC currents compared to the same devices without Kelvin source.

This paper presents an insight into the short circuit (SC) capability of Rohm’s discrete 1.2 kV, 80 mΩ state-of-the-art silicon carbide (SiC) double trench metal-oxide-semiconductor field effect transistor (MOSFET). SC measurements are performed to compare the behavior of Wolfspeed’s similarly rated 1.2 kV, 80 mΩ planar MOSFET with the Rohm trench devices. Short circuit withstand time (SCWT) of both designs under nominal operating conditions at room temperature is measured by performing destructive SC tests.

The main scattering mechanisms reducing the channel mobility and thus the typical performance of a SiC power MOSFET are reviewed. It is demonstrated that the Poisson equation within the drift-diffusion model is able to account for the effects of ionized impurity scattering. Furthermore, a correlation between the size of macro-or nanosteps at the SiC/SiO2 interface and the corresponding fitting parameter within the Lombardi surface roughness model is established. By qualitatively reproducing the typical performance of a commercial SiC power MOSFET a baseline for the TCAD modeling of power MOSFETs is provided.

High-speed optical imaging is used in conjunction with fast electrical measurements to advance the understanding of the development of short circuit failures in silicon carbide power MOSFETs. Special samples are manufactured, which are compatible and comparable to TO-247 packages, but do not have any encapsulation. This allows optical observation of die surface during the test. The information on visible processes on the die allows for a better understanding of the sequence of events leading up to a failure. Imagery of destructive drain-source failures is also obtained, as well as post-failure images of surface and cross-sections. Aluminum metal melting is observed even for very short tests, before electrical indications of damage. The onset and completion of melting are used as information on the temperature of the die surface. Using this data for calibration, a detailed electro-thermal model is then used to simulate the temperature distribution and evolution during the short circuit.

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.