Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs

Abstract

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.

Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

“…This failure path was previously suspected to be thermal lowering of the MOSFET threshold [33]. However, in our prior works [34], we did not observe improvement in avalanche capability by biasing the gate at −10 V to inhibit the MOSFET channel from turning on. "The damage location" observed near the source metallization in posttest decapsulation in [5] is possibly due to the BJT injecting from the source at thermal runways.…”

An investigation of avalanche ruggedness and failure mechanisms of 4H SiC trench MOSFETs in unclamped inductive switching by varying load inductances over a wide range

“…There have been many studies on the avalanche ruggedness of SiC MOSFETs, [16][17][18][19][20][21][22][23][24] including investigations on the dependence of avalanche ruggedness on load inductance under unclamped inductive switching (UIS) tests. [16][17][18][19][20] An avalanche current, which is defined by the maximum peak drain current in the last UIS test prior to the device rupture, shows the highest value of the lowest load inductance used in each study.…”

“…The reduction of V th could create additional paths for leakage currents through MOS channels, resulting in higher lattice temperatures and premature device ruptures. However, research by Nida et al 23) into the dependence of avalanche ruggedness on the negative gate bias concluded that no improvement in ruggedness could be achieved by enhancing the negative gate bias. Hence, theories on the failure mechanism of SiC MOSFETs under UIS conditions remain controversial.…”