Accelerated terrestrial neutron irradiations were performed on different commercial SiC power MOSFETs with planar, trench and double-trench architectures. The results were used to calculate the failure cross-sections and the failure in time (FIT) rates at sea level. Enhanced gate and drain leakage were observed in some devices which did not exhibit a destructive failure during the exposure. In particular, a different mechanism was observed for planar and trench gate MOSFETs, the first showing a partial gate rupture with a leakage path mostly between drain and gate, similar to what was previously observed with heavy-ions, while the second exhibiting a complete gate rupture. The observed failure mechanisms and the post irradiation gate stress (PIGS) tests are discussed for the different technologies.

This paper is presenting a field bus protocol for modular converter systems. It is optimized for minimal cycle times and synchronisation of the modules to ±5 ns. The principle of operation is shown in detail, implemented on an FPGA based prototype system and validated by multiple measurements.

Heavy-ion microbeams are employed for probing the radiation-sensitive regions in commercial silicon carbide (SiC) vertical double-diffused power (VD)-MOSFETs with micrometer accuracy. By scanning the beam spot over the die, a spatial periodicity was observed in the leakage current degradation, reflecting the striped structure of the power MOSFET investigated. Two different mechanisms were observed for degradation. At low drain bias (gate and source grounded), only the gate-oxide (at the JFET or neck region) is contributing in the ion-induced leakage current. For exposures at drain-source bias voltages higher than a specific threshold, additional higher drain leakage current is observed in the p-n junction region. This provides useful insights into the understanding of basic phenomena of single-event effects in SiC power devices.

High sensitivity of SiC power MOSFETs has been observed under heavy ion irradiation, leading to permanent increase of drain and gate leakage currents. Electrical postirradiation analysis confirmed the degradation of the gate oxide and the blocking capability of the devices. At low drain bias, the leakage path forms between drain and gate, while at higher bias the heavy ion induced leakage path is mostly from drain to source. An electrical model is proposed to explain the current transport mechanism for heavy-ion degraded SiC power MOSFETs.

New generations of silicon carbide (SiC) based MOSFETs are commercially available from manufacturers featuring smaller chip size with higher power density demonstrating performance improvement compared to their previous generation counterparts. As the size of the chip is small, the volume available to dissipate energy during short-circuit (SC) like conditions is reduced, leading to increased self-heating of the device. Therefore, the short circuit withstand time (SCWT) is reduced. As a reliability aspect, ruggedness to extreme operating conditions like SC needs to be analyzed for these devices, to improve the design or to design better detection and protection circuits for these MOSFETs when used in specific SC vulnerable applications. In this work, the new third generation 1.2 kV SiC MOSFET from Wolfspeed in a TO-247-4 pin package having a smaller chip size is measured for SC ruggedness. The causes for device failure under different DC-link voltages, gate bias voltages, SC pulse durations and self-heating behavior are analyzed based on the destructive SC tests performed. The device is measured to have an SCWT of 2 µs at a DC-link voltage of 800 V compared to SCWT of 4.5 µs for the second generation 1.2 kV devices with larger chip size and TO-247-3 pin package. The presence of the Kelvin source contact demonstrates higher peak SC currents compared to the same devices without Kelvin source.