Electrothermal modeling of silicon carbide (SiC) power devices is frequently performed to estimate the device temperature in operation, typically assuming a constant thermal conductivity and/or heat capacity of the SiC material. Whether and by how much the accuracy of the resulting device temperature prediction under these assumptions is compromised has not been investigated so far. Focusing on high-temperature operating conditions as found under short circuit (SC), this paper presents a comprehensive analysis of thermal material properties determining the temperature distribution inside SiC power MOSFETs. Using a calibrated technology computer-aided design (TCAD) electrothermal model, it is demonstrated that the temperature prediction of SiC power devices under SC operation when neglecting either the top metallization or the temperature dependence of the heat capacity is inaccurate by as high as 25%. The presented analysis enables to optimize compact electrothermal models in terms of accuracy and computational time, which can be used to assess the maximum temperature of SiC power MOSFETs in both discrete packages and multichip power modules exposed to fast thermal transients. A onedimensional thermal network of a SiC power MOSFET is proposed based on the thermal material properties, the size of the active area of the device, and its thickness. Index Terms-Electrothermal (ET) modeling, short circuit (SC), silicon carbide (SiC), TCAD, thermal conductivity. I. INTRODUCTIONW ITH the ever-increasing requirements for energy saving, the adoption of silicon carbide (SiC) power transistors has been following a growing trend across different power electronic (PE) applications, including electrical vehicles (EVs), EV charging infrastructure, power factor correction, power supply, photovoltaics, uninterruptible power supplies, motor drives, wind, and rail [1]. Increasing the acceptance of the emerging SiC technology in the field of high-frequency, high-temperature, and/or high-power applications needs to be supported by a comprehensive understanding of SiC material properties and their influence on the system performance. Nowadays, multiphysics modeling tools based on the underlying physics of the SiC material are widely employed both in academia and industry to

No abstract

New generations of silicon carbide (SiC) based MOSFETs are commercially available from manufacturers featuring smaller chip size with higher power density demonstrating performance improvement compared to their previous generation counterparts. As the size of the chip is small, the volume available to dissipate energy during short-circuit (SC) like conditions is reduced, leading to increased self-heating of the device. Therefore, the short circuit withstand time (SCWT) is reduced. As a reliability aspect, ruggedness to extreme operating conditions like SC needs to be analyzed for these devices, to improve the design or to design better detection and protection circuits for these MOSFETs when used in specific SC vulnerable applications. In this work, the new third generation 1.2 kV SiC MOSFET from Wolfspeed in a TO-247-4 pin package having a smaller chip size is measured for SC ruggedness. The causes for device failure under different DC-link voltages, gate bias voltages, SC pulse durations and self-heating behavior are analyzed based on the destructive SC tests performed. The device is measured to have an SCWT of 2 µs at a DC-link voltage of 800 V compared to SCWT of 4.5 µs for the second generation 1.2 kV devices with larger chip size and TO-247-3 pin package. The presence of the Kelvin source contact demonstrates higher peak SC currents compared to the same devices without Kelvin source.

Optimized low-inductive layouting of the package interconnections and external PCBs and bus-bars are necessary to benefit from Silicon Carbide (SiC) power devices, which allow inherently very fast switching transitions. In this paper, a comprehensive modeling procedure for highly accurate virtual dynamic characterization of discrete SiC power devices is described taking into account the 3D geometry of the internal and external interconnections of package as input. The modeling requirements are discussed on an example of a commercial 1.2 kV, 80 mΩ SiC Power MOSFET in a standard TO-247 package (Cree C2M0080120D). The software tools, Simplorer, Saber, Q3D and LTSpice, commonly used for modeling and simulation of power modules, are evaluated with respect to their modeling capabilities for SiC devices.

The phenomenon of reduced energy capability of power metal-oxide-semiconductor fieldeffect transistors (MOSFETs) at high avalanche currents is investigated in commercial 1.2-kV 4H-SiC MOSFETs. Unclamped inductive switching (UIS) measurements as well as electrical transport simulations are used to identify the current paths and maximum avalanche currents, providing insight into the design limits. The investigated devices show a reduced energy capability for avalanche current above 52 A due to the latching of the parasitic bipolar junction transistor (BJT). The BJT also limits the maximum switchable current to ≤102 A. Based on the measurements and simulations, a procedure utilizing UIS measurements for identification of design limits is presented.