No abstract

No abstract

No abstract

The Redistributed Chip Package (RCP) is a substrateless embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond BGA and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build-up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build-up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low K device compatibility. The panel is created by attaching device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multi-layer metal RCP packages have passed -40 to 125C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 x 8 array of bumps on a 5 x 5 mm 2 die. Micro Moiré Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported. IntroductionWafer-Level packaging is becoming a very popular method of packaging low to mid-I/O devices for several reasons: cost, size, and ease of testing. Cost is the largest force driving wafer-level packaging.Using batch processing, an entire wafer can be packaged instead of packaging each singulated die. Wafer level packaging reduces packaging steps, eliminates the use of underfill, and allows for centralized processing in the fab. Also, packaging the wafer allows for a high degree of process integration due to the use of fab-type processing such as thin films and lithography which decreases cost. Centralized packaging in the fab also reduces packaging time and inventory, since devices no longer have to be packaged separately between the fab and the assembly houses. Size is also a driving force for wafer-level packaging. The footprint of a WL-CSP is the same as the die. Wafer-level burn-in and test (WLBT) is also driving the industry toward WL-CSP solutions. Test will no longer be necessary before packaging. A completely packaged wafer can be burned-in and tested after the final packaging step resulting in known good packages (KGP). Testing at the wafer level can reduce test costs by as much as 50%, requires less test capital, and reduces the number of test steps.

WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, size, and ease of testing and is ideal for low to mid I/O devices. Peripheral bondpads from the die are redistributed into an area array using a photodielectric and a redistribution metal, eliminating the need for a substrate or interposer. Solder balls are placed onto the redistributed metal bondpads and reflowed, creating a large standoff which improves reliability. The bump structure and pad geometry of the test vehicle was optimized using simulation and validated by experimentation. This WL-CSP technology was evaluated using a 5 x 5 mm 2 die with a 0.5 mm pitch 8 x 8 array of solder bumps. Board level reliability was performed using 1.2 mm thick, 2-layer FR-4 boards with 0.25 mm non-soldermask defined copper pads coated with OSP. Standard thickness WL-CSP wafers are 27-mils. An evaluation was performed to evaluate the potential reliability improvement of WL-CSPs by thinning the wafers. Wafers were thinned down to 4-mils thickness using two techniques. The first method is standard wafer backgrinding. The second is the novel approach of plasma etching, which results in a damage-free surface and improves wafer and die strength. Board level reliability will be presented comparing standard WL-CSPs to those thinned using the aforementioned techniques.

No abstract

No abstract