Improvement in WL-CSP reliability by wafer thinning

Abstract

WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, size, and ease of testing and is ideal for low to mid I/O devices. Peripheral bondpads from the die are redistributed into an area array using a photodielectric and a redistribution metal, eliminating the need for a substrate or interposer. Solder balls are placed onto the redistributed metal bondpads and reflowed, creating a large standoff which improves reliability. The bump structure and pad geometry of the test vehicle was optimized using simulation and validated by experimentation. This WL-CSP technology was evaluated using a 5 x 5 mm 2 die with a 0.5 mm pitch 8 x 8 array of solder bumps. Board level reliability was performed using 1.2 mm thick, 2-layer FR-4 boards with 0.25 mm non-soldermask defined copper pads coated with OSP. Standard thickness WL-CSP wafers are 27-mils. An evaluation was performed to evaluate the potential reliability improvement of WL-CSPs by thinning the wafers. Wafers were thinned down to 4-mils thickness using two techniques. The first method is standard wafer backgrinding. The second is the novel approach of plasma etching, which results in a damage-free surface and improves wafer and die strength. Board level reliability will be presented comparing standard WL-CSPs to those thinned using the aforementioned techniques.

Fast reliability qualification of SiP products

“…Pour l'étude de la fatigue des joints brasés, deux types de contraintes peuvent être mises Figure 26). Keser ont travaillé sur l'amélioration de la fiabilité des WLP par l'amincissement de la puce [78] et ont prouvé qu'amincir la puce augmente la fiabilité ( Figure 27) mais qu'en même temps l'amincissement de la puce change la localisation de la défaillance de la brasure. La zone d'apparition de la fissure dans la brasure est déplacée de la puce vers le PCB.…”

Modeling for reliability of ultra thin chips in a system in package

“…Therefore, it is critical to understand the impact of thinning die to the reliability performance of the product [1]. The ultra thin die could be a potential risk for die cracking if it is done without careful evaluation [4][5]. In this package, a ceramic based heat sink is attached to the lead frame pad through silicone elastomer.…”

Package and board level reliability modeling of advanced CSP pakages for telecommunication applications

“…Kim et al [127] studied the enhancement of solder joint performance using polymer reinforced WLP and Gonzalez et al [128] applied silicon under the bump configuration. The performance of WL-CSP using leadfree solder [129] and thinner wafer [130] were also investigated. The thesis here provides detailed analysis of WL-CSP with 11 design parameters which were not previously investigated by other researchers.…”