Package and board level reliability modeling of advanced CSP pakages for telecommunication applications

2005 7th Electronic Packaging Technology Conference

Luan

et al.

This paper is an overview of applications of CAE (computer-aided-engineering) in design for package and board level reliability of System-in-Package (SiP). CAE is an efficient tool for virtual prototyping of complex SiP to save the development time and cost with understanding on the physics of failures. The paper highlights on five major reliability issues frequently encountered in the development of SiP, such as thermo-mechanical related package failures, matrix package warpage, moisture-induced package failures, board level solder joint reliability under thermal cycling test and drop test. For each individual topic, introduction, brief theory, and an example of application with correlation to experiment are given.

Section: Matrix Package Warpage During Assembly Processesmentioning

confidence: 99%

Section: Board Level Thermal Cycling Solder Joint Reliabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

4-Dimensional Design Analysis and Optimization of System-in-Package

2005 7th Electronic Packaging Technology Conference

Luan

et al.

Development and application of innovational drop impact modeling techniques

Proceedings Electronic Components and Technology, 2005. ECTC '05.

Luan

Due to demand for short time-to-market, drop testing has become a bottleneck for semiconductor and telecommunication industry. Therefore, there is a need for a faster and cheaper solution, i.e. validated drop impact model, which is accurate, reliable, and enables understanding of physics-of-failure for design improvement. Currently, there has been increasing interest and effort by researchers on board level drop test studies by numerical modeling. Several different modeling methods have been developed to satisfy the requirements in package design analysis, product qualification, and impact life prediction. In this paper, for the first time, various advanced drop test modeling techniques developed are systematically introduced, integrated, compared, and recommended for various applications, consisting of analysis type (dynamic vs. static), loading method (free-fall vs. Input-G), and solver algorithm (explicit vs. implicit). Each combination of modeling techniques has its unique advantages, depending on applications. All the models are validated to show excellent first level correlation on the dynamic responses of PCB, second level correlation on the solder joint stress and failure mode, and third level correlation on impact life prediction. Dynamic model is required for accurate drop impact simulation, whereas static model is useful for quick design analysis and optimization. The freefall drop model can be applied to provide fundamental understanding of different drop test conditions, i.e. drop height, contact surface, drop block, felt layer on the impact pulse. Once the impact pulse has been established, the Input-G method can be used as a standard "numerical drop test" to perform design analysis and optimization for product qualification. Implicit solver is an alternative to explicit solver, saving software cost by maintaining only one type of solver, but the technical challenge is greater.

Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA

Proceedings Electronic Components and Technology, 2005. ECTC '05.

Goh

et al.

The semiconductor industry is driving toward lead-free solder due to environmental concern and legislation requirement. The industry has also concluded that SnAgCu solder alloy so far is the best lead-free alternative to SnPb solder. Therefore, most existing and new packages will have to be tested and qualified using lead-free solder. One of the critical concerns is board level solder joint reliability during thermal cycling test. In this paper, the methodology for an absolute life prediction is described for virtual qualification of packages. A good absolute fatigue life prediction requires an appropriate solder creep model and actual test data on packages. Two new sets of lead-free Anand's constants for SnAgCu solder are introduced for creep models. These Anand's creep models are compared with other lead-free and eutectic solder model and the relative design trend is similar. A fatigue corrective factor is introduced to integrate the different solder models together for convenient relative design enhancement with acceptable range of absolute life prediction. These fatigue corrective factors can also be used to compare different finite element modeling assumptions such as element size and solution time step. Subsequently, design analysis is performed to study the effects of 11 key package dimensions and material properties. It is found that the relative design trend for packages with lead-free and eutectic solder is similar. Therefore, the design guidelines established for the previous eutectic solder is still valid for lead-free solder. IntroductionProduct manufacturers are usually concerned of board level solder joint reliability of BGAs during the thermal cycling tests. The typical thermal cycling condition required is -40°C to 125°C to ensure a reliable package performance under the extreme operating conditions. The required fatigue life varies among the customers.However, the process of thermal cycling test is timeconsuming and costly. Therefore, finite element modeling is widely used as an analysis tool for solder joint reliability , especially during the design stage of new package, due to the recent advances in high-speed computer and development of more sophisticated finite element models. There are many approaches used by researchers [36] in the modeling of fatigue life, e.g., stress-based, plastic/creep strain-based, energy-based, and damage accumulation-based. Darveaux methodology [34-35] is a common approach used in the fatigue modeling which applies both energy and damage accumulation-based theories. A life prediction accuracy of ±2x is generally considered adequate due to the complex nature of solder material's creep behavior, and also uncertainty in the board level thermal cycling test.