WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, size, and ease of testing and is ideal for low to mid I/O devices. Peripheral bondpads from the die are redistributed into an area array using a photodielectric and a redistribution metal, eliminating the need for a substrate or interposer. Solder balls are placed onto the redistributed metal bondpads and reflowed, creating a large standoff which improves reliability. The bump structure and pad geometry of the test vehicle was optimized using simulation and validated by experimentation. This WL-CSP technology was evaluated using a 5 x 5 mm 2 die with a 0.5 mm pitch 8 x 8 array of solder bumps. Board level reliability was performed using 1.2 mm thick, 2-layer FR-4 boards with 0.25 mm non-soldermask defined copper pads coated with OSP. Standard thickness WL-CSP wafers are 27-mils. An evaluation was performed to evaluate the potential reliability improvement of WL-CSPs by thinning the wafers. Wafers were thinned down to 4-mils thickness using two techniques. The first method is standard wafer backgrinding. The second is the novel approach of plasma etching, which results in a damage-free surface and improves wafer and die strength. Board level reliability will be presented comparing standard WL-CSPs to those thinned using the aforementioned techniques.
A new wa/er level package has been designed and fabricated in which /he eirlire package can be constructed ut the wafer level using batch processing. Peripheral bondpads are redistributed front the die periphery to an area array using a r.edistribirtion ketal of sputtered aluminum or electropluted copper and a redislrihrrtion dielectric. Redistribution of i~ietal at the wafer level aid7 in eliminating the use of ai1 interposer, or substrate. The redistributed bondpads are plated with the underbump inelallurgy and then bumped using solder ball placenrenr. The solder balls are reflowed onto the wafer creating a large standoff tltal improves reliability. This wafer level chip-scale package (WL-CSP) technology has been evaltrated using a t a l vehicle. which has a 0.5 mrn pitch of air 8 x 8 orroy of bumps on a 5x5 inn? die. The bump structure and package geontetry have been optinihed . using sintulatiori and itdidored by srperinwn!o/ion. The board w e d for reliabilily resting is o I .2 111111 thick, 2-layer FR,4 board with nori-solder?itask defined iandpads with OSP. The landpuds are tlte sairie diameter as IIze redistributed bondpads. Packge and board level reliability data will bepreserited. IntroductionWafer-level packaging is becoming a very popular method of packaging low to mid-110 devices for several rcasoiis: cost, size, and ease of testing. Cost is the largest force driving wafer-levcl packaging. Using batch processing, an entire wafer can be packaged instead of packaging each singulated die. Wafer lcvel packaging rcduces packaging steps, eliminates the usc of underfill, and allows for centralized processing in the fab. Also, packaging the wafer allows for a high degree of process integration due to the use of iabtype processing such as thin tilins and lithography which decreases cost. Centralized packaging in the fab also reduces packaging time aiid inventory, since devices no longer liiive to be packaged separately between the fab and the asscnibly houses:Sizc is also a driving force for wafer-level packoging. The footprint o f a WL-CSP is the same as the die. Wafer-level bum-in and test (WLBT) is also driving the industry toward WL-CSP solutions. Test u d no longer be necessary before packaging. A completely packaged wafer caii be burned-in aiid tcstcd after the final packaging step resulting in known good packages (KGP).Testing at the wafer level can reduce test costs by as much as 50%, requires less test capital, and reduces the number of test steps.One approach to WL-CSP technology is a redistributed ball technology where C5 balls are placed at wafer level to form f i s t and,second level interconnect. Frannhofer IZM has done initial studies on this WL-CSP s t~~c t u r e using stencil printed bumps [I]. In this study, slcncil printed bumps ire replaced with direct ball placement to incroase bump height. This
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