In this paper, ultrathin silicon chip failure mechanism and reliability performance of a system in package (SIP) package are investigated. Advanced finite element analysis (FEA) modeling is carried out to simulate die stress and delamination in the temperature cycling test. Parametric models with different ultrathin die thicknesses, different delamination areas and different bond wire positions are simulated. Temperature cycling modeling results have shown that the thinner die has lower tensile stress than the thicker die. Delamination increases die tensile stress in temperature cycling test. Larger delamination areas in the package induce higher die tensile stress. Comparing with three different delamination models, the model without delamination in the whole package induces lowest die tensile stress, the model with the largest delamination areas at die top surface, aluminum bond wire and lead frame DAP induces the highest die tensile stress. Finally, the modeling results disclose that the bond wire at different position has very limited impact on die stress during temperature cycling test.
IntroductionThe SIP package, which is used for power management has been developed with multiple chips, including power IGBT Mosfet, diode and IC controllers [1][2][3]. To maximize the product performance, the power chips have been made in ultra thin thickness. Ultra thin die minimize the Rds(on), maximize thermal performance, and minimize the board standoff height by allowing the package to be thinner. Therefore, it is critical to understand the impact of thinning die to the reliability performance of the product [1]. The ultra thin die could be a potential risk for die cracking if it is done without careful evaluation [4][5]. In this package, a ceramic based heat sink is attached to the lead frame pad through silicone elastomer. The dimension of ceramic is relative large since all of the power chips are attached to the ceramic layer through lead frame pad. The ceramic layer has much lower thermal expansion coefficient than the mold compound. The big gap of CTE between ceramic and mold compound induces possible delamination at silicon die top surface; aluminum bond wire and lead frame DAP of the package. This could be potential risk for speeding up the die cracking. Therefore, it is very critical to fully investigate the die stress and the delamination in reliability test.In this paper, a 3D delamination model for a power SiP, which considers the initial defects between bond wire and EMC, die and EMC, and DAP and EMC, is built with contact pairs. Parametric models with different ultrathin die thickness, different delamination percentage and different bond wire position are simulated in the temperature cycling test. Three
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