Board level flat and vertical drop impact reliability for wafer level chip scale package

Qian, Richard; Liu, Yong; Kim, Ji‐Hwan; Martin, Stephen R.

doi:10.1109/esime.2011.5765804

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…Smaller welding area leads to worse welding strength, and lower solder joint height has higher dynamic plastic energy density, which greatly reduce the drop test reliability [8]. For this reason, larger ball size is conducive to performance in drop test.…”

Section: B Drop Testmentioning

confidence: 96%

Studies on reliability of a 3D system-in-package device

Jia

Lin

Xiao

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

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To meet the needs of multifunction and miniaturization of modern electronic products, system-inpackage (SiP) has been adapted as one of the most promising packaging technologies. It integrates different chips and devices into one package, which greatly reduces the package size and enhances the performance. However, the relatively complex structure of SiP may cause unexpected failure to the solder joints or silicon chips. In this paper, a 3D package with one larger chip on an FR4 board and four smaller chips on the back side was designed to study the reliability of SiP. The chips were flip-chip bonded to the FR4 board and experienced a set of reliability tests including thermal shock and drop test under JEDEC standards. Moreover, underfill was applied to enhance the reliability of the SiP. The effect of the multiple reflow processes for assembling the complex 3D sample on the reliability of SiP was examined. Failure analysis was carried out to find out the failure mechanism.

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Section: B Drop Testmentioning

confidence: 96%

Studies on reliability of a 3D system-in-package device

Jia

Lin

Xiao

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

View full text Add to dashboard Cite

show abstract

Power Packaging Typical Reliability and Test

Liu

2011

Power Electronic Packaging

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Reliability of fine pitch wafer level packages

Yang

Xiao

et al. 2012

2012 13th International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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Wafer level packaging (WLP) is regarded as one of the most potential single chip packages for its compatibility with wafer fabrication process. As the pitch size of the package becomes lower, the reliability of fme pitch WLP devices is greatly challenged. Finer pitch may result in weaker solder joints, which leads to reliability problems such as fatigue failure, creep deformation and so on. Much work has been done to investigate the reliability of wafer level package above 500 f!m pitch under different conditions such as temperature cycling, thermal shock and drop test, etc. Nevertheless, there are few reports about the reliability of WLP with pitch size less than 500 f!m. In this study, WLP with a size of 5x5 mm 2 and a pitch of 400 f!m were fabricated. Each chip has 144 lead-free SAC105 solder balls in an array of 12x12. The chips are retlowed on Nil Au pads on boards. The chips were experienced a set of reliability tests including temperature cycling, thermal shock and drop test according to JEDEC standards. Furthermore, failure analysis is carried out to study the failure mechanism. Failures are found mostly inside of the solder ball after TC and TS tests, while the drop tests cause more damage to the solder-board and solder-chip interface.

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Board level flat and vertical drop impact reliability for wafer level chip scale package

Cited by 3 publications

References 5 publications

Studies on reliability of a 3D system-in-package device

Studies on reliability of a 3D system-in-package device

Power Packaging Typical Reliability and Test

Reliability of fine pitch wafer level packages

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