Copper films of different thicknesses of 0.2, 0.5, 1 and 2 microns were electroplated on top of the adhesion-promoting barrier layers on <100> single crystal silicon wafers. Controlled Cu grain growth was achieved by annealing films in vacuum.The Cu film microstructure was characterized using Atomic Force Microscopy and Focused Ion Beam Microscopy. Elastic modulus of 110 to 130 GPa and hardness of 1 to 1.6 GPa were measured using the continuous stiffness option (CSM) of the Nanoindenter XP. Thicker films appeared to be softer in terms of the lower modulus and hardness, exhibiting a classical Hall-Petch relationship between the yield stress and grain size. Lower elastic modulus of thicker films is due to the higher porosity and partially due to the surface roughness. Comparison between the mechanical properties of films on the substrates obtained by nanoindentation and tensile tests of the freestanding Cu films is made.
While trends in semiconductor packages continue toward a decrease in overall package size and an increase in functionality and performance requirements, the challenge of maintaining and improving reliability is a critical aspect. In practice, die strength can be adversely affected during various manufacturing processes. The process of die thinning can significantly affect the material's characteristics and reliability. A realistic understanding of the significance of processing on die strength is gained through the study of the actual, processed component. This work outlines a comparative analysis of various thinning processes and their effects on die strength. Characterization of die damage resulting from processing is followed by experimentation utilizing the ball-breaker test methodology to determine die strength with respect to die surface conditions. Through failure analysis of fractured dies, the root causes of die fracture are detected. This information serves as a basis for process selection to meet the trends and needs of a reliable package, and for the development and improvement of existing processes.
A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 x 8 array of bumps on a 5 x 5 mm 2 die. Micro Moiré Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported. IntroductionWafer-Level packaging is becoming a very popular method of packaging low to mid-I/O devices for several reasons: cost, size, and ease of testing. Cost is the largest force driving wafer-level packaging.Using batch processing, an entire wafer can be packaged instead of packaging each singulated die. Wafer level packaging reduces packaging steps, eliminates the use of underfill, and allows for centralized processing in the fab. Also, packaging the wafer allows for a high degree of process integration due to the use of fab-type processing such as thin films and lithography which decreases cost. Centralized packaging in the fab also reduces packaging time and inventory, since devices no longer have to be packaged separately between the fab and the assembly houses. Size is also a driving force for wafer-level packaging. The footprint of a WL-CSP is the same as the die. Wafer-level burn-in and test (WLBT) is also driving the industry toward WL-CSP solutions. Test will no longer be necessary before packaging. A completely packaged wafer can be burned-in and tested after the final packaging step resulting in known good packages (KGP). Testing at the wafer level can reduce test costs by as much as 50%, requires less test capital, and reduces the number of test steps.
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