This paper presents a new SOI BCD technology at the 0.18 m node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25m .mm 2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability. Depletion NMOS, LV&HV diodes, 5V zener diode, high gain BJT, excellent matching well resistor, capacitors, top thick Copper Metallization option, embedded memory (OTP, CEEPROM, etc.) are also offered on this comprehensive technology platform.
A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific onresistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.
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