Optimized design of spiral inductors for Si RF IC's

Xiong, Xinhong; Fusco, Vincent; Toner, B.

doi:10.1109/hfpsc.2000.874082

Cited by 5 publications

(3 citation statements)

References 11 publications

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“…Over the last few years, several techniques have been proposed to optimize the physical layout of silicon-based spiral inductors. One popular approach adopted by many research groups is to optimize layout of the inductor by making use of existing lumped-element RF SPICE models [3]- [6]. Such convenient optimization algorithms are however limited by the validity of these SPICE models in making accurate predictions of the inductors' behavior at high frequencies when their physical design parameters such as core diameter, conductor spacing and width are modified accordingly.…”

Section: Introductionmentioning

confidence: 99%

Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications

Sia¹,

Ong

Chan

et al. 2005

IEEE Trans. Electron Devices

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A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.

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Section: Introductionmentioning

confidence: 99%

Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications

Sia¹,

Ong

Chan

et al. 2005

IEEE Trans. Electron Devices

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“…Most of the research studies published in the literature utilized limited test structures to develop scalable inductor models. They also fail to ensure identical inductance values when making device performance comparisons at different application frequencies [11][12][13][14]. On the contrary, this research work has a huge test element group of 102 inductors spanning wide-ranging physical design parameters of 1.5 to 6.5-turn, widths from 4 to 32 µm and core diameters from 30 to 180 µm, to comprehensively test the proposed extraction strategy and model development methodology for the symmetrical inductors.…”

Section: Model Verification and Evaluation Of This Workmentioning

confidence: 99%

Modeling and Layout Optimization Techniques for Silicon-Based Symmetrical Spiral Inductors

Sia¹,

Lim²,

Ong³

et al. 2013

PIER

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Abstract-A scalable and highly accurate RF symmetrical inductor model (with model error of less than 5%) has been developed from more than 100 test structures, enabling device performance versus layout size trade-offs and optimization up to 10 GHz. Large conductor width designs are found to yield good performance for inductors with small inductance values. However, as inductance or frequency increases, interactions between metallization resistive and substrate losses render the use of large widths unfavorable as they consume silicon area and degrade device performance. These findings are particularly important when exploiting the cost-effective silicon-based RF technologies for applications with operating frequencies greater than 2.5 GHz.

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“…has been used for the inductor model development. Nonetheless, even with these concerns, three other papers [32] - [34] with more efficient optimization algorithms that made use of the same physical spiral inductor model were subsequently published.…”

Section: Q-factor Enhancement Using Layout Optimizationmentioning

confidence: 99%

Device design, characterization and modeling of inductors and interconnects for RFIC applications

Sia¹

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Optimized design of spiral inductors for Si RF IC's

Cited by 5 publications

References 11 publications

Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications

Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications

Modeling and Layout Optimization Techniques for Silicon-Based Symmetrical Spiral Inductors

Device design, characterization and modeling of inductors and interconnects for RFIC applications

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